The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs). While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.
3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of IEEE Computer Society.
Please note that early (discounted) registration for the workshop (and for ITC) expires on Friday, October 5!
Yervant Zorian - General Chair
700 East Middlefield Road
Mountain View, CA 94043-4033, USA
Tel.: +1 (650) 584-7120
Erik Jan Marinissen - Program Chair
B-3001 Leuven, Belgium
Tel.: +32 (0)16 28-8755
Fax: +32 (0)16 28-1515
Said Hamdioui - Program Chair
Delft University of Technology
2628CD, Delft, the Netherlands
Tel.: +31 (0)15 278-3643