Third IEEE International Workshop on
Testing Three-Dimensional Stacked Integrated Circuits
3D-Test
in conjunction with ITC / Test Week 2012
November 8-9, 2012 - Disneyland Hotel Anaheim, California, USA
Program Committee

S. Adham - TSMC (CAN)
V. Agrawal - Auburn Univ. (US)
S. Bhatia - Oasys (US)
C. Bullock - Texas Instruments (US)
K. Chakrabarty - Duke Univ. (US)
S. Chakravarty - LSI (US)
V. Chickermane - Cadence (US)
E. Cormack - DfT Solutions (UK)
A. Crouch - Asset Intertech (US)
J. Foerstel - Altera (US)
S.K. Goel - TSMC (US)
G. Fleeman - Advantest (US)
M.-L. Flottes - LIRMM (FR)
P. Franzon - NC State Univ. (US)
M. Higgins - Analog Devices (IRL)
C.-L. Hsu - ITRI (TW)
S.-Y. Huang - NTHU (TW)
R. Kapur - Synopsys (US)
M. Knox - IBM (US)
M. Laisne - Qualcomm (US)
P. Lebourg - ST Microelectronics (FR)
S. Lecomte - ST-Ericsson (FR)
H.-H. Lee - Georgia Tech (US)
K.H. Lee - GigaLane (KR)
A. Leong - MicroProbe (US)
I. Loi - Universita di Bologna (IT)
M. Loranger - FormFactor (US)
C. Mayor - Presto Engineering (FR)
T. McLaurin - ARM (US)
K. Parker - Agilent Technologies (US)
S. Pateras - Mentor Graphics (US)
B. Patti - Tezzaron Semiconductor (US)
F. Pöhl - Intel (DE)
M. Ricchetti - AMD (US)
D. Rishavy - TEL Test Systems (US)
T. Thärigen - Cascade Microtech (DE)
E. Volkerink - Advantest (US)
Y. Xie - Penn. State Univ. / AMD (US)
Q. Xu - Chinese Univ. Hong Kong (HK)

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