Fifth IEEE International Workshop on
Testing Three-Dimensional Stacked Integrated Circuits
3D-Test
in conjunction with ITC / Test Week 2014
October 23-24, 2014 - Hyatt Hotel at Olive 8 Seattle, WA, USA
Program Committee

S. Adham - TSMC (CAN)
V. Agrawal - Auburn Univ. (US)
S. Bhatia - Oasys (US)
K. Chakrabarty - Duke Univ. (US)
S. Chakravarty - Avago Technologies (US)
K.Y. Chung - Samsung (KR)
C.J. Clark - Intellitech (US)
E. Cormack - DfT Solutions (UK)
A. Cron - Synopsys (US)
A. Crouch - Asset Intertech (US)
D. Domke - Texas Instruments (US)
M.-L. Flottes - LIRMM (FR)
P. Franzon - NC State Univ. (US)
S.K. Goel - TSMC (US)
S. Hamdioui - TU Delft (NL)
M. Higgins - Analog Devices (IRL)
C.-L. Hsu - ITRI (TW)
S.-Y. Huang - NTHU (TW)
M. Hutner - Teradyne (CAN)
H. Jun - SK hynix (KR)
S. Kameyama - Fujitsu (JP)
M. Knox - IBM (US)
M. Laisne - Qualcomm (US)
S. Lecomte - Intel (DE)
K.H. Lee - GigaLane (KR)
C.M. Li - NTU (TW)
M. Loranger - FormFactor (US)
A. Majumdar - Xilinx (US)
T.M. Mak - GlobalFoundries (US)
T. McLaurin - ARM (US)
B. Nadeau-Dostie - Mentor Graph. (US)
C. Papameletis - Cadence (US)
B. Patti - Tezzaron Semiconductor (US)
M. Ricchetti - AMD (US)
S. Shaikh - Broadcom (US)
T. Thärigen - Cascade Microtech (DE)
P. Vivet - CEA-Leti (FR)
M. Wahl - Univ. Siegen (DE)
Q. Xu - Chinese Univ. Hong Kong (HK)

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