 | Test Synthesis with Alternative Graphs (R.Ubar).
IEEE Design and Test of Computers. Spring, 1996,
pp.48-59 |  |  |  |
| | Teaching Test and Design for Testability with
TURBO-TESTER Software (G.Jervan, A.Markus, P.Paomets,
J.Raik, R.Ubar) Proc. of the 3rd Workshop on Mixed
Design of Integrated Circuits and Systems, Lodz, May
1996, pp 589-594. |  | | |
| | Combining Symbolic Techniques with Topological Approach
in Test Generation (R.Ubar).
Proc. of the 3rd Workshop on Mixed Design of Integrated
Circuits and Systems, Lodz, May 1996, pp 377-382. | | | |
| Multi-Level Test Generation and Fault Diagnosis for
Finite State Machines (R.Ubar, M.Brik). Lecture Notes in
Computer Science No 1150. Dependable Computing - EDCC-2.
Springer-Verlag, 1996, pp.264-281 | | | |
| | Low-Cost CAD System for Teaching Digital Test (G.Jervan, A.Markus, P.Paomets, J.Raik, E.Ivask, R.Ubar). Microelectronics Education. World Scientific Publishing
Co. Pte. Ltd. 1996, pp.185-188 | | | |
| | Electronics Competence Centre and Research in Digital
Test at the Technical University of Tallinn (R.Ubar).
Proc. of the 14th NORCHIP Conference, Helsinki,
4-5 November 1996, pp. 134-141 | | | |
| | Fault Model and Test Synthesis for RISC-processors (G.Jervan, A.Markus, J.Raik, R.Ubar).
Proc. of the 5th Biennial Baltic Electronics Conference
Tallinn, October 7-11, 1996, pp.229-232 | | | |
| Test Generation for Finite State Machines (R.Ubar, M.Brik). Proc. of the 5th Biennial Baltic Electronics Conference
Tallinn, October 7-11, 1996, pp.233-236 | | | |
| | A Constraint-Driven Gate-Level Test Generation (J.Raik, R.Ubar, G.Jervan,
H.Krupnova).
Proc. of the 5th Biennial Baltic Electronics Conference
Tallinn, October 7-11, 1996, pp.237-240 | | | |
