Gert Jervan      Research      Publications      Teaching      Other
December 10, 2016   [10:45]

Gert Jervan
Akadeemia tee 15a
12618 Tallinn, Estonia
Tel: (+372) 620 2261
skype: gert.jervan

Tippkeskus CEBE

Kompetentsikeskus CREDES

Sardsüsteemide õppe- ja teaduslabor


Gert Jervan

New office location starting from March 18, 2013: Akadeemia tee 15a, 5th floor, office 527.

Gert Jervan is a professor of dependable computer systems at the Department of Computer Engineering at Tallinn University of Technology. Since September 1st, 2013 he is also a Dean at the Faculty of Information Technology.

He received his M.Sc. degree from Tallinn University of Technology in 1998 and Tech. Lic. and Ph. D. degrees from Linköping University (LIU), Sweden in 2002 and 2005, respectively. He was previously with the Embedded Systems Laboratory (ESLAB) at Linköping University, Sweden

He belongs to the management committee of the Estonian centre of excellence in research CEBE (Centre for Integrated Electronic Systems and Biomedical Engineering) and was one of the coordinators of the EU FP7 REGPOT project CREDES (Centre of Research Excellence in Dependable Embedded Systems). In 2006-2011 he was a member of the Estonian Science Foundation's Expert Commission for Physical Sciences and Engineering. He is also one of the authors of the Strategic Plan of Tallinn University of Technology 2011-2015.

He was a special sessions chair and one of the main organizers of the 2010 Diagnostic Services in Network-on-Chips workshop (co-located with DAC 2010). Recently he was serving as a vice program chair of Norchip 2008 (November 17-18, 2008), general chair of the 19th EAEEEIE Annual Conference (June 29 - July 2, 2008) and was one of the organizers of the DATE 2008 Friday Workshop Impact of Process Variability on Design and Test. In 2011 he was the organizer of two special sessions: Power and Thermal Issues in 3D ICs at the IEEE International Workshop on Impact of Low Power Design on Test and Reliability (LPonTR), May 26-27, Trondheim, Norway and Dependability in multiprocessor and reconfigurable SoCs at the 6th International Workshop on Reconfigurable Communication Centric Systems-on-Chip (ReCoSoC 2011), June 20-22, Montpellier, France. He was a Program Chair of ReCoSoC 2013. Recently he was also a general organizer of the 2013 HiPEAC Autumn Computing Systems Week and a program chair of the 2014 European Workshop on Microelectronics Education.

Up to date CV (incl. publications) from the ETIS database (link opens in a new window).

Research Interests

  • Dependability and fault tolerance of embedded systems
  • Networks-on-Chip (NoCs): system-level design, fault tolerance
  • Test and Diagnostics of Digital Systems:
    • High-Level Testability and Design for Test (DfT)
    • Built-in self-test (BIST) and its different flavors
    • SoC & NoC Test

Research Activities

  • Estonian centre of excellence in research CEBE (Centre for Integrated Electronic Systems and Biomedical Engineering)
  • EU FP7 REGPOT project CREDES (Centre of Research Excellence in Dependable Embedded Systems).

  • Previous projects:
    • Estonian Science Foundation grant: Test and Fault Tolerance of Network-on-Chip Based Systems. 2006-2009. Accepted proposal (pdf).
    • STRINGENT project: Hybrid BIST methodology for complex electronic systems
    • Member of SNDFT - Swedish Network of Design for Test Research
    • INTELECT project: Testability-Driven Hardware/Software Codesign
    • COTEST - Testability Support in a Co-design Environment (Project of the IST Programme)
    • VILAB: Microelectronics Virtual Laboratory for Cooperation in Research and Knowledge Transfer
    • STES - Self-Test in Embedded Systems



  • Undergraduate:
    • IAF0530 - Dependability and fault tolerance
    • IAF0320 - Computer Systems Engineering

  • Graduate:

  • Graduate Student Supervision:
    • Mihkel Tagel, Fault tolerance and reliability of networks-on-chip (Kiipvõrkude veakindlus ja usaldusväärsus). PhD 2012. Now with TD Baltic.
    • Deniss Nikiforov, Reliability management in complex embedded systems (Töökindluse tagamine keerukates sardsüsteemides), 2008-...
    • Erkki Moorits, Specification methods for architectures, hardware and software of modern mission-critical hardware-software systems (Meetodite leidmine kaasaegsetel tehnoloogilisetel platvormidel põhinevate ohutuskriitiliste riistvara/tarkvarasüsteemide arhitektuuri, riistvara ja tarkvara optimaalse tehnilise spetsifikatsiooni koostamiseks), 2009-...
    • Mairo Leier, Scalable Open Platform for Reliable Sensorics (Laiendatav avatud platvorm usaldusväärsete sensorite jaoks), 2010-...

  • Master Thesis Supervision:
    • Mehrdad Bagheri Majdabadi, Fault Tolerant Scheduling of Mixed-Critical Applications on Multi-Processor Platforms
    • Zahra Jafari, Scheduling of Systems with Mixed-Criticality Requirements
    • Radomir Shebek, Memory consistency and cache coherency in networks on chip based multi-core systems, 2012
    • Mairo Leier, Kehalähedase sensorvõrgustiku süsteemi arendus. Südame rütmi jälgimise süsteem (Body Area Network System Development. Heart Rate Monitoring System), 2010.
    • Auli Lepp, Temperatuuri-teadlik testide planeerimine 3D arhitektuuriga kiipidel (Temperature-aware test scheduling for 3D architectures), 2009.
    • Deniss Nikiforov. Automatic generation of task graphs. Tallinn University of Technology, 2008.
    • Vassili Zdanov. Extraction of task-level parallelism. Tallinn University of Technology, 2008.
    • Peeter Mäeker. XY-marsruutimisalgoritmil põhineva kiipvõrgu testimise simulaator (XY-routing algorithm based NoC test simulator). Tallinn University of Technology, 2007.
    • Mihkel Tagel. Deterministlik võrguliikluse generaator kiipvõrgu simulaatorile (Deterministic traffic generator for NoC simulator). Tallinn University of Technology, 2006.
    • Tatjana Shchenova. Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment. Tallinn University of Technology, 2005.
    • Maksim Jenihhin. Test Time Minimization for Hybrid BIST of Systems-on-Chip Tallinn University of Technology, 2003.
    • Yuanhui Sun. Automatic behavioral test generation by using a constraint solver. Linköping University, 2002.

  • Previous Teaching (at LiU):
    • TDTS43 - Computer Networks and Distributed Systems (Development of lab exercises, lab assistant - 1999, 2000)
    • TDDB12 - Concurrent Programming and Operating Systems (Development of lab exercises, lab assistant - 1999)
    • TTIT61 - Concurrent Programming and Operating Systems (Course assistant - 2000)
    • TDDB63 - Concurrent Programming and Operating Systems (Lab assistant - 2000, 2001)
    • TDTS80 - Computer Aided Design of Electronics (Course assistant - 2001)
    • TDTS01 - Computer Aided Design of Electronics (Development of lab exercises, course assistant, lecturer - 2002-2004)


  • Senior member of the IEEE, IEEE Computer Society, IEEE CS Test Technology Technical Council. Chair of the Estonian CS Chapter.
  • HiPEAC member.
  • Member of the European Association for Education in Electrical and Information Engineering council
  • Member of the Association for Computing Machinery (ACM)
  • Member of the EU thematic network EIE-Surveyor Managing team (2005-2009)

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