List of publications

2009

  1. Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar. PSL Assertion-Checking Using Temporally Extended High-Level Decision Diagrams. Journal of Electronic Testing: Theory and Applications, Springer Science, 2009.
  2. Jaan Raik, Vineeth Govind, Raimund Ubar. Design-for-Testability-Based External Test and Diagnosis of Mesh-like NoCs. IET Computers and Digital Techniques, Vol. 3, Issue 5, pp. 476-486, September 2009.
  3. Maksim Jenihhin, Jaan Raik, Anton Chepurov, Uljana Reinsalu, Raimund Ubar. High-Level Decision Diagrams based Coverage Metrics for Verification and Test. Proceedings of 10th IEEE Latin American Test Workshop, pp. 1-6, IEEE, 2009
  4. Raimund Ubar, Sergei Kostin, Jaan Raik. Investigations of the Diagnosibility of Digital Networks with BIST. 10th IEEE Latin-American Test Workshop – LATW 2009, Rio de Janeiro, Brazil, March. 2-5, 2009, pp.1-6.
  5. Sergei Devadze, Raimund Ubar, Jaan Raik, Artur Jutman. Parallel Exact Critical Path Tracing Fault Simulation with Reduced Memory Requirements. 4th IEEE Int. Conf. on Design and Technology of Integrated Systems in Nanoscale Era – DTIS’09, Cairo, Egypt, April 6-7, 2009, pp. 155-160.
  6. Raimund Ubar, Jaan Raik, Anton Karputkin, Mati Tombak. Synthesis of High-Level Decision Diagrams for Functional Test Pattern Generation. 16th International Conference Mixed Design of Integrated Circuits and Systems, Lodz, 25-27 June 2009.
  7. Maksim Jenihhin, Jaan Raik, Anton Chepurov, Uljana Reinsalu, Raimund Ubar. Code Coverage Analysis for Concurrent Programming Languages Using High-Level Decision Diagrams. 12th European Workshop on Dependable Computing (EWDC 2009), Toulouse, France, May 14-15, 2009.
  8. Raimund Ubar, Sergei Kostin, Jaan Raik. Block-Level Model-Free Debug and Fault Diagnosis in Digital Systems. Proceedings of the 12th Euromicro Conference on Digital System Design (DSD) Architectures, Methods and Tools, IEEE Computer Society, Patras, Greece, pp. 229-232, August 27th - 29th, 2009.
  9. Raimund Ubar, Sergei Kostin, Jaan Raik. Combined Fault-Model Free Cause-Effect and Effect-Cause Fault Diagnosis in Block-Level Digital Networks. Proceedings of the 1st Asia Symposium on Quality Electronic Design (ASQED'09), IEEE, Kuala Lumpur, Malaysia, pp. 385-390, July 15-16, 2009.
  10. Sergei Kostin, Raimund Ubar, Jaan Raik, Margit Aarna, Marina Brik, Heinz-Dieter Wuttke. Teaching Research in the Laboratory Using Diagnosis Environment for Digital Systems. 20th EAEEIE Conference on Innovation in Education for Electrical and Information Engineering, Valencia, Spain, pp.1-4, June 22-24, 2009.
  11. R.Ubar, S.Kostin, A.Jutman, J.Raik, H.-D.Wuttke. DIAGNOZER: A Laboratory Tool for Teaching Research in Diagnosis of Electronic Systems. Proceedings of the 2009 International Conference on Microelectronic Systems Education (MSE'09), San Francisco, pp. 12-15, July 25.-26, 2009.
  12. Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar. Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams. IEEE East-West Design & Test Symposium, pp.13-16, Moscow, Sept. 18-21, 2009.
  13. Anton Karputkin, Raiund Ubar, Jaan Raik, Mati Tombak. Canonical Representations of High Level Decision Diagrams. Estonian Journal of Engineering, Vol. 15, Issue 4, 2009.
  14. Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar. Application of High-Level Decision Diagrams for Simulation-Based Verification Tasks. Estonian Journal of Engineering, Vol. 15, Issue 4, 2009.
  15. R.Ubar, D.Mironov, J.Raik, A.Jutman. Structurally Synthesized Multiple Input BDDs for Simulation of Digital Circuits. Proceedings of IEEE International Conference on Electronics, Circuits and Systems. Hammamet, Tunisia, Dec. 13-16, 2009.
  16. Raimund Ubar, Jaan Raik, Dmitri Mironov, Teet Evartson, Elmet Orasson. Teaching Diagnostic Modeling of Digital Systems with Decision Diagrams. Proceedings of the 12th IASTED International Conference on Computers and Advanced Technology in Education – CATE 2009, St. Thomas, US Virgin Islands, Nov. 22-24, 2009.

2008

  1. Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar. Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation. Proceedings of the 13th IEEE European Test Symposium, IEEE Computer Society, pp. 61-68, Los Alamitos, USA, May, 2008.
  2. Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman. Parallel Fault Backtracing for Calculation of Fault Coverage. The 13th Asia and South Pacific Design Automation Conference (ASP-DAC 2008), IEEE, pp. 667-672, January 21 - 24, 2008, Seoul, Korea.
  3. Jaan Raik, Hideo Fujiwara, Raimund Ubar, Anna Krivenko. Untestable Fault Identification in Sequential Circuits Using Model-Checking. The 17th Asian Test Symposium (ATS 2008), IEEE, pp. 667-672, November 24-27, 2008, Sapporo, Japan.
  4. Artur Jutman, Igor Aleksejev, Jaan Raik, Raimund Ubar. Reseeding Using Compaction of Pre-Generated LFSR Sub-Sequences. The 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), IEEE, pp. , Malta, August 31 - September 3, 2008.
  5. Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee. Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. IEEE International Symposium on Electronic Design, Test and Applications (DELTA), pp. 222-227, January 23 - 25, 2008, Hongkong.
  6. Jaan Raik, Raimund Ubar, Taavi Viilukas, Maksim Jenihhin. Mixed Hierarchical-Functional Fault Models for Targeting Sequential Cores. Elsevier Journal of Systems Architecture, Vol. 54, Issue 3-4, pp. 465-477, Elsevier, March-April 2008.
  7. Raimund Ubar, Sergei Kostin, Jaan Raik. Fault Diagnosis in Emebedded Digital Systems with BIST. Journal: Embedded Hardware Design (Microprocessors and Microsystems), Vol. 32, Issue 5-6, pp. 279-287, Elsevier, August 2008.
  8. Andres Mellik, Jaan Raik. An XML-based Test Development and Deployment Framework for Mixed-Signal and Digital Devices. Proceedings of the IEEE AUTOTESTCON, Salt Lake City, USA, Sept. 8-11, 2008.
  9. Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz. Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. Proceedings of the 11th Euromicro Conference on Digital System Design (DSD) Architectures, Methods and Tools, IEEE Computer Society, pp. 729-734, Parma, Italy, September 3-5, 2008.
  10. Eero Ivask, Jaan Raik, Raimund Ubar. Distributed Approach for Genetic Test Generation In the Field of Digital Electronics. 2nd International Symposium on Intelligent Distributed Computing - IDC'2008 , Springer Verlag, September 18-19, 2008, Catania, Italy.
  11. Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee. Fast Code Coverage Analysis using High-Level Decision Diagrams. Proceedings of the 11th IEEE Workshop on Design and Diagnostics of Electronic Systems (DDECS), IEEE Computer Society, April, 2008.
  12. Eero Ivask, Jaan Raik, Raimund Ubar. Web-Based Framework for Parallel Distributed Test. Proceedings of the 11th IEEE Workshop on Design and Diagnostics of Electronic Systems (DDECS), IEEE Computer Society, April, 2008.
  13. Jaan Raik, Hideo Fujiwara, Anna Krivenko. RT-Level Identification of Potentially Testable Initialization Faults. The Ninth IEEE Workshop on RTL and High Level Testing (WRTLT 2008), IEEE, pp. 667-672, November 27-28, 2008, Sapporo, Japan.
  14. Raimund Ubar, Jaan Raik, Artur Jutman, Maksim Jenihhin, Martin Instenberg, Heinz-Dietrich Wuttke. Modeling Microprocessor Faults on High-Level Decision Diagrams. 2nd Workshop on Dependable and Secure Nanocomputing June 27, 2008, Anchorage, AK, USA.
  15. Vineeth Govind, Jaan Raik. Design-for-Testability for Application of External Test Patterns in a NoC. 2nd Workshop on Diagnostiic Services in Network-on-Chips - Test, Debug, and On-Line Monitoring, In conjunction with Design Automation Conference (DAC), Anaheim, USA, June 9, 2008.
  16. Igor Aleksejev, Artur Jutman, Jaan Raik, Raimund Ubar. Application of Sequential Test Set Compaction to LFSR Reseeding. 26th Norchip Conference, IEEE, 17-18 November 2008, Tallinn, Estonia.
  17. Raimund Ubar, Sergei Kostin, Jaan Raik. Embedded Diagnosis in Digital Systems. 26th International Conference on Microelectronics (MIEL 2008) , IEEE, pp. 421-424, Nis, Serbia, 11-14 May 2008.
  18. Jaan Raik, Raimund Ubar, Artur Jutman, Igor Aleksejev. A Scalable Static Test Set Compaction Method for Sequential Circuits. 9th IEEE Latin American Test Workshop , February 17-20, 2008, Puebla, Mexico.
  19. Jaan Raik, Raimund Ubar, Maksim Jenihhin, Anton Chepurov. PSL Assertion Checking with Temporally Extended High-Level Decision Diagrams. 9th IEEE Latin American Test Workshop , February 17-20, 2008, Puebla, Mexico.
  20. Raimund Ubar, Sergei Kostin, Jaan Raik. Built-In Self Diagnosis with Multiple Signature Analyzers in Digital Systems. 9th IEEE Latin American Test Workshop , February 17-20, 2008, Puebla, Mexico.
  21. Anton Chepurov, Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Jaan Raik, Raimund Ubar, Taavi Viilukas. Automatic Generation of EFSMs and HLDDs for Functional ATPG. 11th Biennial Baltic Electronics Conference , IEEE, pp. 143-146, October 6-8, 2008, Laulasmaa, Estonia.
  22. Raimund Ubar, Jaan Raik, Artur Jutman, Maksim Jenihhin, Marina Brik, Martin Istenberg, Heinz-Dieter Wuttke. Diagnostic Modeling of Microprocessors with High-Level Decision Diagrams. 11th Biennial Baltic Electronics Conference , IEEE, pp. 147-150, October 6-8, 2008, Laulasmaa, Estonia.
  23. Maksim Jenihhin, Jaan Raik, Raimund Ubar, Anton Chepurov. On reusability of verification assertions for testing. 11th Biennial Baltic Electronics Conference , IEEE, pp. 151-154, October 6-8, 2008, Laulasmaa, Estonia.
  24. Raimund Ubar, Sergei Kostin, Jaan Raik. Calculation of the Diagnosibility of Digital Circuits without Using Fault Models. 11th Biennial Baltic Electronics Conference , IEEE, pp. 159-162, October 6-8, 2008, Laulasmaa, Estonia.
  25. Andres Mellik, Jaan Raik. Test Development and Deployment Tool-set for Mixed-Signal and Digital Devices. 11th Biennial Baltic Electronics Conference , IEEE, pp. 163-166, October 6-8, 2008, Laulasmaa, Estonia.
  26. Karina Minakova, Uljana Reinsalu, Anton Chepurov, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Peeter Ellervee. High-Level Decision Diagram Manipulations for Code Coverage Analysis. 11th Biennial Baltic Electronics Conference , IEEE, pp. 207-210, October 6-8, 2008, Laulasmaa, Estonia.
  27. Jaan Raik, Maksim Jenihhin, Anton Chepurov, Uljana Reinsalu, Raimund Ubar. APRICOT: a Framework for Teaching Digital Systems Verification. 19th EAEEIE Annual Conference , IEEE, pp. 172-177, June 29 - July 2, 2008, Tallinn, Estonia.
  28. Eero Ivask, Jaan Raik, Artur Jutman, Raimund Ubar. Web-Based Framework for Distributed Remote Laboratory in the Field of Digital System Test. 19th EAEEIE Annual Conference , IEEE , pp. 182-187, June 29 - July 2, 2008, Tallinn, Estonia.

2007

  1. Peeter Ellervee, Jaan Raik, Raimund Ubar, Kalle Tammemäe. FPGA-based fault emulation of synchronous sequential circuits. IET Computers and Digital Techniques, volume 1, issue 2, pp. 70-76, March 2007.
  2. Jaan Raik, Raimund Ubar, Vineeth Govind. Test Configurations for Diagnosing Faulty Links in NoC Switches. Formal Proceedings of the 12th IEEE European Test Symposium, IEEE press, pp. 29-34, Freiburg, Germany, May 20-24, 2007.
  3. Raimund Ubar, Sergei Devadze, Jaan Raik. Ultra Fast Parallel Fault Analysis on Structural BDDs. Formal Proceedings of the 12th IEEE European Test Symposium, IEEE press, pp. 131-136, Freiburg, Germany, May 20-24, 2007.
  4. Raimund Ubar, Jaan Raik, Helena Kruus, Harri Lensen, Teet Evartson. Diagnostic Modelling of Digital Systems with Binary and High-Level Decision Diagrams, Proc. 14th European Conference on Mathematics for Industry (ECMI 2006), Publisher: Springer, 10-14 July 2006, Leganes, Spain (pp 1-5).
  5. Jaan Raik, Vineeth Govind, Raimund Ubar. An External Diagnosis method for Network-on-a-Chip. IEEE/ACM Design Automation and Test in Europe Workshop on Diagnostic Services in Networks-on-Chips – Test, Debug and On-Line Monitoring, April 16-20, Nice, France.
  6. Jaan Raik, Raimund Ubar, Anna Krivenko, Margus Kruus. Hierarchical Identification of Untestable Faults in Sequential Circuits, Proceedings of the 10th IEEE Euromicro Conference on Digital Systems Design DSD2007, IEEE Computer Society, pp. 668-671, 27-31 August, 2007, Lübeck, Germany.
  7. Raimund Ubar, Sergei Kostin, Jaan Raik, Teet Evartson, Harri Lensen. Fault Diagnosis in Integrated Circuits with BIST, Proceedings of the 10th IEEE Euromicro Conference on Digital Systems Design DSD2007, IEEE Computer Society, pp. 604-610, 27-31 August, 2007, Lübeck, Germany.
  8. Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar. Assertion Checking with PSL and High-Level Decision Diagrams. Proceedings of the IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07), October 12-13, 2007, Beijing, P.R.China
  9. Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold Pleskacz, Michal Rakowski. Layout to Logic Defect Analysis for Hierarchical Test Generation. DDECS'07 - 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, pp. 35-40, Kraków, Poland, April 11-13, 2007.
  10. Raimund Ubar, Sergei Kostin, Jaan Raik. Fault Diagnosis in the BIST Environment Based on Bisection of Detected Faults. 8th IEEE Latin American Test Workshop, p. 6, March 11 - 14, 2007, Cuzco, Peru.
  11. Andres Mellik, Jaan Raik. Comparative Mixed-signal Test Method and Toolset. IEEE International Workshop on Open Source Test Technology Tools (IOST3), May 9-10, 2007 Berkeley, California, USA.
  12. Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman. Parallel Fault Backtracing for Calculation of Fault Coverage. International Conference on Microelectronics, Devices and Materials MIDEM, Workshop on electronic testing, pp. 165-170, September 12-14, 2007, Bled, Slovenia.
  13. Raimund Ubar, Sergei Kostin, Jaan Raik, Margus Kruus. Experimental Comparison of Different Diagnosis Algorithms in the BIST Environment. IASTED Conference on Applied Simulation and Modelling - ASM 2007, ACTA Press, August 29-31, 2007, Palma de Mallorca, Spain
  14. Giuseppe Di Guglielmo, Franco Fummi, Maksim Jenihhin, Graziano Pravadelli, Jaan Raik, Raimund Ubar. On the Combined Use of HLDDs and EFSMs for Functional ATPG. 5th IEEE East-West Design & Test Symposium (EWDTS), Yerevan, Armenia, September 7-10, 2007 .

2006

  1. Sergei Devadze, Jaan Raik, Artur Jutman, Raimund Ubar. Fault Simulation with Parallel Critical Path Tracing for Combinational Circuits Using Structurally Synthesized BDDs. Proceedings of the IEEE Latin American Test Workshop, Buenos Aires, Argentine, pp. 97-102, March 2006.
  2. Raimund Ubar, Teet Evartson, Margus Kruus, Harri Lensen, Jaan Raik. Diagnostic Modelling of Digital Systems with Multi-Level Decision Diagrams. Proceedings of the IASTED Conference, ACTA Press, Montreal, pp. 207-212, May 24.-26, 2006.
  3. Jaan Raik, Raimund Ubar, Taavi Viilukas. High-Level Decision Diagram based Fault Models for Targeting FSMs. Proceedings of the 9th IEEE Euromicro Conference on Digital Systems Design DSD2006, Cavtat, pp. 353-358, Aug. 31 - Sep. 2, 2006.
  4. Vineeth Govind, Jaan Raik, Raimund Ubar. A Generic Synthesizable NoC Switch with a Scalable Testbench. Proceedings of the Baltic Electronics Conference, Laulasmaa, 2006.
  5. Knut Hermann, Jaan Raik, Maksim Jenihhin. TTBist: a DfT Tool for Enhancing Functional Test for SoC. Proceedings of the Baltic Electronics Conference, Laulasmaa, 2006.
  6. Raimund Ubar, Marina Brik, Artur Jutman, Jaan Raik, Tomas Bengtsson, Shashi Kumar. Functional Test Generation for Finite State Machines. Proceedings of the Baltic Electronics Conference, Laulasmaa, 2006.
  7. Peeter Ellervee, Jaan Raik, Kalle Tammemäe, Raimund Ubar. Environment for FPGA Based Fault Emulation. Proceedings of the Estonian Academy of Sciences. Engineering, (12/3-2), pp. 323-335, 2006.
  8. Jaan Raik, Vineeth Govind, Raimund Ubar. An External Test Approach for Network-on-a-Chip Switches. Proceedings of the IEEE Asian Test Symposium 2006, Fukuoka, Japan, pp. 437-442, Nov. 2006.

2005

  1. Jaan Raik, Tanel Nõmmeots, Raimund Ubar. A New Testability Calculation Method to Guide RTL Test Generation. Journal of Electronic Testing: Theory and Applications, Springer Science, Vol. 21, No. 1, pp.71-82, February 2005.
  2. Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman. Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. Springer Lecture Notes in Computer Science, Proceedings of the 5th European Dependable Computing Conference, Springer, pp. 332-344, 2005.
  3. Joachim Sudbrock, Raimund Ubar, Jaan Raik, Wieslaw Kuzmicz,Witold Pleskacz. DOT: New Deterministic Defect-Oriented ATPG Tool. Proceedings of the IEEE European Test Symposium, IEEE Computer Society, Los Alamitos, USA, pp. 96-101, May 22-25, 2005.
  4. Jaan Raik, Raimund Ubar, Joachim Sudbrock, Wieslaw Kuzmicz, Witold Pleskacz. Deterministic Defect-Oriented Test Generation for Digital Circuits. 6th IEEE Latin-American Test Workshop LATW2005, pp. 325-330, Salvador de Bahia, Brazil, March 30 - April 2, 2005.
  5. Yuri A. Skobtsov, Dmitri E. Ivanov, Vadim Y. Skobtsov, Raimund Ubar, Jaan Raik. Evolutionary Approach to Test Generation for Functional BIST. Informal Proceedings of the IEEE European Test Symposium, pp. 151-155, Tallinn, Estonia, May 22-25, 2005.
  6. Artur Jutman, Raimund Ubar, Jaan Raik. Generic Interconnect BIST for Network-on-Chip. Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems (DDECS) Workshop, pp. 224-227, Sopron, Hungary, April 13-16, 2005.
  7. Marcel Balaz, Maria Fischerova, Elena Gramatova, Artur Jutman, Zdenek Kotasek, Ondrej Novak, Tomaš Pikula, Jaan Raik, J.Strnadel, Raimund Ubar, J.Zahradka. Testing Tools for Training and Education. 12th International Conference Mixed Design of Integrated Circuits and Systems, Kraków, 22-25 June 2005, pp.671-676.
  8. Raimund Ubar, Elmet Orasson, Jaan Raik, Heinz-Dieter Wuttke. Teaching Advanced Test Issues in Digital Electronics. 6th IEEE International Conference on Information Technology Based Higher Education and Training. July 7-9, 2005, Santo Domingo,  pp. S2B-5 - S2B-10.
  9. Artur Jutman, Raimund Ubar, Jaan Raik. New Built-In Self-Test Scheme for SoC Interconnect. Invited session on advanced interconnect architectures. 9th World Multi-Conference on Systemics, Cybernetics and Informatics. July 10-13, 2005, Orlando, Florida, USA, vol.4, pp.19-24.
  10. Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar. Improved Fault Emulation for Synchronous Sequential Circuits. 8th IEEE Euromicro conference on Digital Systems Design DSD2005. Porto, Aug. 30 - Sept. 3, 2005, pp.72-78.
  11. Artur Jutman, Jaan Raik, Raimund Ubar, Vladislav Vislogubov. An Educational Environment for Digital Testing: Hardware, Tools, and Web-based Runtime Platform. 8th IEEE Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.412-419.
  12. Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold Pleskacz. Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. 8th IEEE Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.79-82.
  13. Jaan Raik, Maksim Jenihhin, Rain Adelbert. Sequential Circuits BIST Synthesis from Signal Specifications. IEEE Norchip Conference, Oulu, Finland, Nov. 21-22, 2005, pp.196-199.
  14. Raimund Ubar, Margit Aarna, Helena Kruus, Jaan Raik. High Quality Test Generation for Digital Systems. Romanian Journal of Information Science and Technology, Publishing House of the Romanian Academy, Volume 8, Number 1, 2005, pp. 73-84.

2004

  1. Jaan Raik, Raimund Ubar. Enhancing Hierarchical ATPG with a Functional Fault Model for Multiplexers. Proc. of IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems DDECS, pp.219-222, Stara Lesna, Slovakia, April 18-21, 2004.
  2. Jaan Raik, Raimund Ubar. Targeting Conditional Operations in Sequential Test Pattern Generation. Digest of papers of the European Test Symposium, pp. 17-18, Ajaccio, France, May 23-26, 2004.
  3. Eero Ivask, Jaan Raik, Raimund Ubar, Andre Schneider. Web-Based Environment Using Digital Electronics Test Tools. Virtual Enterprises and Collaborative Networks, IFIP 18th World Computer Congress, Kluwer Academic Publishers, pp. 435-442, Tolouse, France, Aug. 22-27, 2004.
  4. Raimund Ubar, Tatjana Vassiljeva, Jaan Raik, Artur Jutman, Mati Tombak, Ahti Peder. Optimization of Structurally Synthesized BDDs. Proc of the 4th IASTED International Conference on Modelling, Simuation, and Optimization MSO 2004, pp. 234-240, Kauai, Hawaii, USA, Aug. 17-19, 2004.
  5. Artur Jutman, Ahti Peder, Jaan Raik, Mati Tombak, Raimund Ubar. Structurally synthesized binary decision diagrams. 6th International Workshop on Boolean Problems, pp. 271-278, Freiberg, Germany, Sept. 23-24, 2004.
  6. Jaan Raik,  Anna Krivenko, Raimund Ubar. Comparative Analysis of Sequential Circuit Test Generation Approaches. Proc. of the Baltic Electronic Conference, pp. 225-228,  Tallinn, Estonia, Oct. 3-6, 2004.
  7. Marina Brik, Jaan Raik, Raimund Ubar, Eero Ivask. On Using Genetic Algorithm for Test Generation. Proc. of the Baltic Electronic Conference, pp. 233-236, Tallinn, Estonia, Oct. 3-6, 2004.
  8. Vladislav Vislogubov, Artur Jutman, Helena Kruus, Elmet Orasson, Jaan Raik, Raimund Ubar. Diagnostic Software with WEB Interface for Teaching Purposes. Proc. of the Baltic Electronic Conference, pp. 255-258, Tallinn, Estonia, Oct. 3-6, 2004.
  9. Peeter Ellervee, Jaan Raik, Valentin Tihhomirov. Environment for Fault Simulation Acceleration on FPGA. Proc. of the Baltic Electronic Conference, pp. 217-220, Tallinn, Estonia, Oct. 3-6, 2004.
  10. Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, Kalle Tammemäe. Evaluating Fault Emulation on FPGA. Field-Programmable Logic and Applications. 14th International Conference , FPL 2004. Eds. J.Becker, M.Platzner, S.Vernalde, Springer Verlag, pp. 354-363, Antwerp, Belgium, Aug. 30 – Sept. 1, 2004.
  11. Jaan Raik, Elmet Orasson, Raimund Ubar. Sequential Circuits BIST with Status Bit Control. 11th International Conference on Mixed Design of Integrated Circuits and Systems MIXDES, pp. 507-510, Szczecin, Poland, June 24-26, 2004.
  12. Raimund Ubar, Natalja Mazurova, Julia Smahtina, Elmet Orasson, Jaan Raik. HYFBIST: Hybrid Functional Built-In Self-Test in Microprogrammed Data-Paths of Digital Systems. 11th International Conference on Mixed Design of Integrated Circuits and Systems MIXDES, pp. 497-502, Szczecin, Poland, June 24-26, 2004.
  13. Marina Brik, Jaan Raik, Raimund Ubar, Eero Ivask. GA-based Test Generation for Sequential Circuits. Proc. of the East-West Design & Test Workshop - EWDTW'04, pp. 30-34, Yalta, Alushta, Ukraine, July-Sept. 2004.
  14. Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar. Fast Fault Emulation for Synchronous Sequential Circuits. Proc. of the East-West Design & Test Workshop - EWDTW'04, pp. 35-40, Yalta, Alushta, Ukraine, July-Sept. 2004.
  15. Jaan Raik, Vineeth Govind, Raimund Ubar. RTL Test Point Insertion for Sequential Circuits. Proc. of the International Workshop on Testability Assessment (IWoTA), Rennes, France, Nov. 2, 2004.
  16. Raimund Ubar, Margit Aarna, Marina Brik, Jaan Raik. High-Level Fault Modeling in Digital Systems. Synergies between Information Processing and Automation, International Conference IWK, Shaker Verlag, Vol.2, pp. 486-491, Ilmenau, Germany, September 27-30, 2004.
  17. Eero Ivask, Artur Jutman, Elmet Orasson, Jaan Raik, Raimund Ubar, Heinz-Dieter Wuttke. Research Environment for Teaching Digital Test. Synergies between Information Processing and Automation, International Conference IWK, Shaker Verlag, Vol.2, pp. 468-473, Ilmenau, Germany, September 27-30, 2004.
  18. Raimund Ubar, Margit Aarna, Helena Kruus, Jaan Raik. How to Generate High Quality Tests for Digital Systems. IEEE International Semiconductor Conference, CAS’2004,  Vol. 2, pp. 459-462, Sinaia, Romania, Oct. 4-6, 2004.
  19. Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, Raimund Ubar. FPGA Based Fault Emulation of Synchronous Sequential Circuits. Proc. of the IEEE NORCHIP Conference,  Oslo, Norway, November 8-9, 2004.

2003

  1. Jaan Raik, Tanel Nõmmeots, Raimund Ubar. New Method of Testability Calculation to Guide RT-Level Test Generation. Proc. of 4th IEEE Latin-American Test Workshop - LATW2003, pp.46-51, Natal, Brazil, February 16-19, 2003.
  2. Raimund Ubar, Jaan Raik. Testing Strategies for Networks on Chip. In "Networks on Chip" by A.Jantsch, H.Tenhunen. Kluwer Academic Publishers, 2003, pp. 131-152.
  3. Raimund Ubar, Jaan Raik, Bjorn Klüver. Algorithms for hierarchical fault simulation in digital systems. MIXDES Conference, pp. 530-535, Lodz, Poland, June 26-28, 2003.
  4. Andre Schneider, K.-H.Diener, G.Elst, Raimund Ubar, Eero Ivask, Jaan Raik. Integration of Digital Test Tools to the Internet-Based Environment MOSCITO. World Multiconference on Systemics, Cybernetics and Informatics. Vol. VIII, pp. 136-141, Orlando, Florida, July 27-30, 2003.
  5. Jaan Raik, Raimund Ubar. DECIDER: A System for Hierarchical Test Pattern Generation. East-West Design & Test Conference - EWDTC'03, Scientific-Technical Journal Radioelectronics and Informatics, No. 3 (24), pp. 40-45, July-Sept. 2003.
  6. Margit Aarna, Eero Ivask, Artur Jutman, Elmet Orasson, Jaan Raik, Raimund Ubar, Vladislav Vislogubov, Heinz-Dieter Wuttke. Turbo Tester - Diagnostic Package for Research and Training. East-West Design & Test Conference - EWDTC'03, Scientific-Technical Journal Radioelectronics and Informatics, No. 3 (24), pp. 69-73, July-Sept. 2003.
  7. Peeter Ellervee, Jaan Raik, Valentin Tihhomirov. Fault Emulation on FPGA: A Feasibility Study. Proc. of the Norchip Conference, Riga, Latvia, Nov. 11-12, 2003.
  8. Jaan Raik, Rein Raidma, Raimund Ubar. Explorations in Low Area Overhead DfT Techniques for Sequential BIST. Proc. of the Norchip Conference, Riga, Latvia, Nov. 11-12, 2003.
  9. Andrei Mekler, Jaan Raik. Multiple-Objective Backtrace for Solving Test Generation Constraints. Proc. of the International Symposium on System-on-Chip, Tampere, Finland, Nov. 19-21, 2003.

2002

  1. Tatiana Cibakova, Maria Fischerova, Elena Gramatova, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar. Hierarchical test generation for combinational circuits with real defects coverage, Journal of Microelectronics Reliability. Pergamon Press. Vol  42/7, pp 1141-1149, July 2002.
  2. Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik. Multi-Level Fault Simulation of Digital Systems on Decision Diagrams, IEEE Workshop on Electronic Design, Test and Applications - DELTA02, pp.86-91, Christchurch, New Zealand, 29-31 January 2002.
  3. Andre Schneider, Eero Ivask, Peter Miklos, Jaan Raik, Karl-Heinz Diener, Raimund Ubar, Tatiana Cibáková, Elena Gramatová. Internet-based Collaborative Test Generation with MOSCITO. IEEE Proc. of  Design Automation and Test in Europe - DATE02, pp. 221-226, Paris, March  4-8, 2002.
  4. Jaan Raik, Artur Jutman, Raimund Ubar. Exact Static Compaction of Sequential Circuit Tests using branch-and-bound and Search State Registration, IEEE European Test Workshop, Corfu, Greece, May 26-29, 2002.
  5. Artur Jutman, Jaan Raik, Raimund Ubar. SSBDD Model: Advantageous Properties and Efficient Simulation Algorithms, IEEE European Test Workshop, Corfu, Greece, May 26-29, 2002.
  6. Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik. Defect-Oriented Mixed-Level Fault Simulation in Digital Systems. Facta Universitatis (Nis), Ser.: Elec. Energ. Vol.15, No.1, pp.123-136, April 2002.
  7. Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik. Mixed-Level Defect Simulation in Data-Paths of Digital Systems. 23rd Int. Conf. on Microelectronics, Vol.2, pp.617-620, Nis, Yugoslavia, May 12-15 2002.
  8. Artur Jutman, Jaan Raik, Raimund Ubar. On Efficient Logic-Level Simulation of Digital Circuits Represented by the SSBDD Model. 23rd Int. Conf. on Microelectronics, Vol.2, pp.621-624, Nis, Yugoslavia, May 12-15 2002.
  9. Tanel Nõmmeots, Jaan Raik, Raimund Ubar. Testability Analysis for Efficient Register-Transfer Level Test Generation. Proc. of the MIXDES Conference, pp. 555-558, Wroclaw, Poland, June 20-22, 2002.
  10. Artur Jutman, Jaan Raik, Raimund Ubar. SSBDDs: Advantageous Model and Efficient Algorithms for Digital Circuit Modeling, Simulation and Test. Proc. of the 5th International Workshop on Boolean Problems. pp. 157-166, Sept. 19-20, 2002, Freiberg, Germany.
  11. Jaan Raik, Artur Jutman, Raimund Ubar. Fast Static Compaction of Tests Composed of Independent Sequences: Basic Properties and Comparison of Methods. Proc. of the ICECS 2002 Conference. Vol. II, pp. 445-448, Sept. 15-18, 2002, Dubrovnik, Croatia.
  12. Raimund Ubar, Artur Jutman, Elmet Orasson, Jaan Raik, Teet Evartson, Heinz-Dieter Wuttke. Internet-Based Software for Teaching Test of Digital Circuits. Microelectronics Education. Proc. of the 4th European Workshop on Microelectronics Education. Marcombo publishers, pp. 317-320, May 23-24, 2002, University of Vigo, Spain.
  13. Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik. Test Cover Calculation in Digital Systems with Word-Level Decision Diagrams. Proc. of the Tomsk State University, Vol. No. 1 (II). pp. 315-319, Sept. 2002, Tomsk, Russia.
  14. Andre Schneider , Karl-Heinz Diener , Gert Jervan , Zebo Peng , Jaan Raik ,Raimund Ubar , Thomas Hollstein , Manfred Glesner. High-Level Synthesis and Test in the MOSCITO-Based Virtual Laboratory. Proc. of the Baltic Electronic Conference, Oct. 7-9, 2002, Tallinn, Estonia.
  15. Jaan Raik, Artur Jutman, Raimund Ubar. Exact Static Compaction of Independent Test Sequences. Proc. of the Baltic Electronic Conference, Oct. 7-9, 2002, Tallinn, Estonia.
  16. Andre Schneider, Karl-Heinz Diener, Günter Elst, Eero Ivask, Jaan Raik, Raimund Ubar. Internet-Based Testability-Driven Test Generation in Virtual Environment MOSCITO, Proc. of the International Workshop on IP-Based SoC Design, Oct. 30-31, 2002, Grenoble, France.
  17. Raimund Ubar, Jaan Raik, Tanel Nõmmeots. Testability Guided Hierarchical Test Generation with Decision Diagrams, Proc. of the NORCHIP Conference, Nov. 11-12, 2002, Copenhagen, Denmark.

2001

  1. Raimund Ubar, Wieslaw Kuzmicz, Witold Pleskacz, Jaan Raik. Defect-Oriented Fault Simulation and Test Generation in Digital Circuits, 2nd International Symposium on Quality of Electronic Design, pp. 365-371, San Jose, California, USA, March 26-28, 2001.
  2. Jaan Raik, Artur Jutman, Raimund Ubar. Fast and Efficient Static Compaction of Test Sequences Based on Greedy Algorithms. Proc. of the Design and Diagnostics of Electronic Circuits and Systems DDECS'2001 Conference, pp. 117-122, Györ, Hungary, April 18-20, 2001.
  3. Tatiana Cibaková, Elena Gramatova, Wieslaw Kuzmicz, Witold Pleskacz, Jaan Raik, Raimund Ubar. Defect-Oriented Library Builder for Functional Test Generation, Proc. of the Design and Diagnostics of Electronic Circuits and Systems DDECS'2001 Conference, pp. 163-168, Györ, Hungary, April 18-20, 2001.
  4. Eero Ivask, Raimund Ubar, Jaan Raik. Internet Based Test Generation and Fault Simulation, Proc. of the Design and Diagnostics of Electronic Circuits and Systems DDECS'2001 Conference, pp. 57-60, Györ, Hungary, April 18-20, 2001.
  5. Jaan Raik, Artur Jutman, Raimund Ubar. Fast Static Compaction of Test Sequences Using Implications and greedy Search, Digest of European Test Workshop, pp. 207-210, Stockholm, May 29 - June 1, 2001.
  6. Tatiana Cibakova, Maria Fischerova, Elena Gramatova, Wieslaw Kuzmicz, Witold Pleskacz, Jaan Raik, Raimund Ubar. Defect-Oriented Test Generation Using Probabilistic Estimation. MIXDES 01, pp.131-136, Zakopane, Poland, June 21-23, 2001.
  7. Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik. Hierarchical Fault Simulation in Digital Systems, Proceedings of  Int. Symp. on Signals, Circuits and Systems SCS 2001, pp.181-184, Iasi, Romania, July 10-11, 2001.
  8. Margit Aarna, Jaan Raik, Raimund Ubar. Parallel Fault Simulation in Digital Circuits, Proc. of 42th International Scientific Conference of Riga Technical University, pp.91-94, Riga, October 11-13, 2001.
  9. Mykola Blyzniuk, I.Kazymyra, Wieslaw Kuzmicz, W.A.Pleskacz, Jaan Raik, Raimund Ubar. Probabilistic Analysis of CMOS Physical Defects in VLSI Circuits for Test Coverage Improvements, Journal of Microelectronics Reliability. Pergamon Press. Vol  41/12, pp 2023-2040, Dec. 2001.
  10. Wieslaw Kuzmicz, Witold Pleskacz, Jaan Raik, Raimund Ubar. Module Level Defect Simulation in Digital Circuits, Proceedings of the Estonian Academy of Sciences, No 7/4, pp.253-268, 2001.
  11. Jaan Raik. Hierarchical Test Generation for Digital Circuits Represented by Decision Diagrams, PhD thesis, TTU press, Tallinn 2001.

2000

  1. Mykola Blyzniuk, Tatiana Cibakova, Elena Gramatova, Wieslaw Kuzmicz, M.Lobur, Witold Pleskacz, Jaan Raik, Raimund Ubar. Hierarchical Defect-Oriented Fault Simulation for Digital Circuits. Formal Proceedings of the IEEE European Test Workshop, pp. 69-74, Cascais, Portugal, May 23-26, 2000.
  2. Raimund Ubar, Jaan Raik. Efficient Hierarchical Approach to Test Generation for Digital Systems, International Symposium on Quality of Electronic Design, pp. 189-195, San Jose, California, USA, March 20-22, 2000.
  3. Adam Morawiec, Raimund Ubar, Jaan Raik. Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. Proceedings of the DATE Conference, p. 743, Paris, France, March 27-30, 2000.
  4. Raimund Ubar, Adam Morawiec, Jaan Raik. Vector Decision Diagrams for Simulation of Digital Systems. Proc. of the DDECS'2000 Conference, pp. 44-51, Smolenice, Slovak Republic, April 5-7, 2000.
  5. M.Blyzniuk, T.Cibakova, Elena Gramatova, Wieslaw Kuzmicz, M.Lobur, Witold Pleskacz, Jaan Raik, Raimund Ubar. Hierarchical Defect-Oriented Fault Simulation for Digital Circuits. IEEE European Test Workshop, pp. 151-156, Cascais, Portugal, May 23-26, 2000.
  6. Eero Ivask, Jaan Raik, Raimund Ubar. Fault Oriented Test Pattern Generation for Sequential Circuits Using Genetic Algorithms. IEEE European Test Workshop, pp. 319-320 Cascais, Portugal, May 23-26, 2000.
  7. Raimund Ubar, Adam Morawiec, Jaan Raik. Back-Tracing and Event-Driven Techniques in High-Level Simulation with Decision Diagrams, Proc. of the IEEE ISCAS'2000 Conference, Vol. 1, pp. 208-211, Geneva, Switzerland, May 28-31, 2000.
  8. Jaan Raik, Raimund Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers. Vol. 16, No. 3, pp. 213-226, June, 2000.
  9. Mykola Blyzniuk, Tatiana Cibakova, Elena Gramatova, Wieslaw Kuzmicz, M. Lobur, Witold Pleskacz, Jaan Raik, Raimund Ubar. Defect Oriented Fault Coverage of 100% Stuck-at Fault Test Sets. Proc. of the 7th International Conference on Mixed Design of Integrated Circuits and Systems. Gdynia (Poland), June 15-17, 2000, pp.511-516.
  10. Raimund Ubar, Adam Morawiec, Jaan Raik. High-Level Decision Diagrams for Simulation Performance, Proc. of the World Multiconference on Systemics, Cybernetics and Informatics, Vol. IX Industrial Systems, pp. 62-67, Orlando, Florida, USA, July 23-26, 2000.
  11. Jaan Raik. Greedy Alternative for the Static Compaction of Sequential Circuit Test Sequences. Baltic Electronics Conference, Tallinn, Estonia, Oct. 8-11, 2000.
  12. Marina Brik, Jaan Raik, Raimund Ubar. Hierarchical Fault Simulation for Finite State Machines. Baltic Electronics Conference, Tallinn, Estonia, Oct. 8-11, 2000.
  13. Raimund Ubar, Elmet Orasson, Jaan Raik, Heinz-Dieter Wuttke. Combining Learning, Training and Research in Laboratory Course for Design and Test. Baltic Electronics Conference, Tallinn, Estonia, Oct. 8-11, 2000.
  14. Adam Morawiec, Jaan Raik, Raimund Ubar. Simulation of Digital Systems with High-Level Decision Diagrams. Baltic Electronics Conference, Tallinn, Estonia, Oct. 8-11, 2000.
  15. Eero Ivask, Jaan Raik, Raimund Ubar. Fault-Oriented Test Pattern Generation for Sequential Circuits Using Genetic Algorithms. Baltic Electronics Conference, Tallinn, Estonia, Oct. 8-11, 2000.

1999

  1. Jaan Raik, Raimund Ubar. Sequential Circuit Test Generation Using  Decision Diagram Models, Proceedings of the DATE Conference, pp. 736-740, Munich, Germany, March 9-12, 1999.
  2. Raimund Ubar, Adam Morawiec, Jaan Raik. Cycle-based Simulation with Decision Diagrams, Proceedings of the DATE Conference, pp. 454-458, Munich, Germany, March 9-12, 1999.
  3. Karl-Heinz Diener, Günter Elst, Eero Ivask, Jaan Raik, Raimund Ubar. FPGA Design Flow with Automated Test Generation, Proc. of the 11th Workshop on Test Technology and Reliability of Circuits and Systems, pp. 120-123, Potsdam, Germany, Feb 28-Mar 2, 1999.
  4. Raimund Ubar, Jaan Raik. Hierarchical Test Generation for Complex Digital Systems with Control and Data Processing Parts, SEMICON Singapore 1999 Technical Symposium, pp. 43-52, Singapore, May 3-6 1999.
  5. Jaan Raik, Raimund Ubar. High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation, Compendium of Papers of the European Test Workshop, 5 p., Konstanz, Germany, May 25-28, 1999.
  6. Jaan Raik, Raimund Ubar. High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation, Proc. of the European Test Workshop, pp. 84-89, Konstanz, Germany, May 25-28, 1999.
  7. Antti Markus, Jaan Raik, Raimund Ubar. Fast and Efficient Static Compaction of Test Sequences Using Bipartite Graph Representation, Proc. of the Second Electronic Circuits and Systems Conference ECS'99, pp. 17-20, Bratislava, Slovakia, Sept. 6-8, 1999.
  8. Gert Jervan, Petru Eles, Zebo Peng, Jaan Raik, Raimund Ubar. High-Level Test Synthesis with Hierarchical Test Generation, Proc. of the NORCHIP Conference, pp. 291-296, Oslo, Norway, Nov. 8-9, 1999.

1998

  1. Marina Brik, Gert Jervan, Antti Markus, Priidu Paomets, Jaan Raik, Raimund Ubar. Hierarchical Test Generation for Digital Systems. Mixed Design of Integrated Circuits and Systems, Kluwer Academic Publishers, pp. 131-136, 1998.
  2. Gert Jervan, Antti Markus, Priidu Paomets, Jaan Raik, Raimund Ubar. A CAD System for Teaching Digital Test. Microelectronics Education. Proc. of the 2nd European Workshop on Microelectronics Education, Kluwer Academic Publishers, pp. 287-290, Noordwijkerhout, the Netherlands, May 14-15, 1998.
  3. Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar. Hierarchical Test Generation with Multi-Level Decision Diagram Models. Proc. of the 7-th IEEE North Atlantic Test Workshop, pp. 26-33, West Greenwich, RI, USA, May 28-29, 1998.
  4. Jaan Raik, Raimund Ubar. Feasibility of Structurally Synthesized BDD Models for Test Generation. Compendium of Papers of the European Test Workshop, pp. 145-146, Barcelona, May 27-29, 1998.
  5. Gert Jervan, Antti Markus, Raimund Ubar, Jaan Raik. VHDL based Test Generation System. Proc. of the 5th Int. Conf. on Electronic Devices and Systems, pp. 145-148, Brno, Czech Republic, June 11-12, 1998.
  6. Jaan Raik, Raimund Ubar. Test Generation with Structurally Synthesized BDD Models. Proc. of the 5th Int. Conf. on Electronic Devices and Systems, pp. 66-69, Brno, Czech Republic, June 11-12, 1998.
  7. Gert Jervan, Antti Markus, Raimund Ubar, Jaan Raik. Mixed Level Deterministic - Random Test Generation for Digital Systems. Proc. of the MIXDES'98 Conf., pp. 335-340, Lodz, Poland, June 18-20, 1998.
  8. Raimund Ubar, Jaan Raik. Hierarchical test generation for digital systems based on combining bottom-up and top-down approaches. Proc. of the World Multiconference SCI'98 / ISAS'98, pp. 374-381, Orlando, USA, July 12-16, 1998.
  9. Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar. DECIDER: A Decision Diagram based Hierarchical Test Generation System. Proc. of the DDECS'98 Conference, pp. 269-273, Szczyrk, Poland, September 2-4, 1998.
  10. Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar. A Decision Diagram based Hierarchical Test Generator. Proc. of the BEC'98 Conference, pp. 159-162, Tallinn, Estonia, Oct. 7-9, 1998.
  11. Antti Markus, Jaan Raik, Raimund Ubar. Test Set Minimization using Bipartite Graphs. Proc. of the BEC'98 Conference, pp. 175-178, Tallinn, Estonia, Oct. 7-9, 1998.
  12. Eero Ivask, Jaan Raik, Raimund Ubar. Comparison of Genetic and Random Techniques for Test Pattern Generation. Proc. of the BEC'98 Conference, pp. 163-166, Tallinn, Estonia, Oct. 7-9, 1998.
  13. Raimund Ubar, Jaanus Heinlaid, Lembit Raun, Jaan Raik. Calculation of Testability Measures on Structurally Synthesized Binary Decision Diagrams. Proc. of the BEC'98 Conference, pp. 179-182, Tallinn, Estonia, Oct. 7-9, 1998.

1997

  1. Gert Jervan, Antti Markus, Priidu Paomets, Jaan Raik, Raimund Ubar. CAD Software for Digital Test and Diagnostics. Proc. of the International Conference on Design and Diagnostics of Electronic Circuits and Systems '97. pp. 35-40, Beskydy Mountains, Czech Republic, May 12-16, 1997.
  2. Raimund Ubar, Jaan Raik. Multi-Valued Simulation With Binary Decision Diagrams. Compedium of Papers of IEEE European Test Workshop. pp. 28-29, Cagliari, Italy, May 28-30, 1997.
  3. Marina Brik, Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar. A Hierarchical Automatic Test Pattern Generator Based on Using Alternative Graphs. Proc. of the 4-th International Workshop on Computer Aided Design of Modern Devices and ICs. pp. 415-420, Poznan, Poland, June 12-14, 1997.
  4. Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar. Automatic Test Generation System for VLSI. Proc. of the 1-st Electronic Circuits and Systems Conference. pp. 255-258, Bratislava, Slovakia, Sep. 4-5, 1997.
  5. Gert Jervan, Antti Markus, Priidu Paomets, Jaan Raik, Raimund Ubar. A Set of Tools for Estimating Quality of Built-In Self-Test in Digital Circuits. Proc. of the International Symposium on Signals Circuits and Systems. pp. 362-365, Iasi, Romania, Oct. 2-3, 1997.
  6. Alfredo Benso, Paolo Prinetto, Mauricio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar. Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. pp. 212-216, Paris, France, October 20-22, 1997.
  7. Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar. Assembling Low-Level Tests to High-Level Test Frames. Proc. of the IEEE 15th NORCHIP Conf. pp. 275-280, Tallinn, Estonia, Nov. 10-11, 1997.
  8. Marina Brik, Gert Jervan, Antti Markus, Priidu Paomets, Jaan Raik, Raimund Ubar. Mixed-Level Test Generator for Digital Systems. Proc. of the Estonian Acad. of Sci. Engng. Vol. 3, No. 4, pp. 269-280, Tallinn, Estonia, 1997.

1996

  1. Raimund Ubar, Jaan Raik, Priidu Paomets, Eero Ivask, Gert Jervan, Antti Markus. Low-Cost CAD System for Teaching Digital Test. Proc. of the 1st European Workshop on Microelectronics Education. p. 48, Villard de Lans, France, Feb. 5-6, 1996.
  2. Raimund Ubar, Jaan Raik, Priidu Paomets, Eero Ivask, Gert Jervan, Antti Markus. Low-Cost CAD System for Teaching Digital Test. Microelectronics Education. World Scientific Publishing Co. Pte. Ltd. pp. 185-188, Grenoble, France, Feb. 1996.
  3. Gert Jervan, Antti Markus, Priidu Paomets, Jaan Raik, Raimund Ubar. Teaching Test and Design with Turbo Tester Software. Proc. of the 3rd Advanced Training Course: Mixed Design of Integrated Circuits and Systems MIXDES'96. pp. 589-594, Lodz, Poland, May 30 - June 1, 1996.
  4. Jaan Raik, Raimund Ubar, Gert Jervan, Helena Krupnova. A Constraint-Driven Gate-Level Test Generator. Proc. of the 5-th Baltic Electronics Conference. pp. 237-240, Tallinn, Estonia, Oct. 1996.
  5. Raimund Ubar, Antti Markus, Gert Jervan, Jaan Raik. Fault Model and Test Synthesis for RISC Processors. Proc. of the 5-th Baltic Electronics Conference. pp. 229-232, Tallinn, Estonia, Oct. 1996.
  6. Jaan Raik, Priidu Paomets. Test Synthesis from Register-Transfer Level Descriptions. Proc. of the 5-th Baltic Electronics Conference. pp. 311-314, Tallinn, Estonia, Oct. 1996.

1995

  1. Priidu Paomets, Jaan Raik, Raimund Ubar. A CAD System for ASIC Test and Design. Exhibition 'Search for Partners' at the Special Session 'European Cooperation in Science, Technology and Education. Workshop on Sampling Theory and Applications. Riga, Latvia, Sept. 1995.

1994

  1. Raimund Ubar, Ahto Buldas, Priidu Paomets, Jaan Raik, Viljar Tulit. A PC-based CAD System for Training Digital Test. Proc. of the V EUROCHIP Workshop on VLSI Design Training. pp. 152-157, Dresden, Germany, Oct. 1994.
  2. Raimund Ubar, Eero Ivask, Priidu Paomets, Jaan Raik. A CAD System for Teaching Digital Test. Proc. of the 4-th Baltic Conference. pp. 369-372, Tallinn, Estonia, Oct. 1994.

Articles on Popular Science Topics

  1. Jaan Raik. IEEE Euroopa 10 Testisümpoosion Tallinnas. TTÜ ajaleht Mente et Manu, 18.01.2006, p.6.
  2. Jaan Raik. Chip Design in the Baltics: Fact or Fiction?. Baltic IT&T Review, No. 3 (38), 2005, pp.44-46.
  3. Raimund Ubar, P.Prinetto, Jaan Raik. 10th European Test Symposium. IEEE Design & Test of Computers, September-October 2005, pp. 480-481.
  4. Jaan Raik. Digitaalkiipide projekteerimine ja test - teadus, tehnoloogia või kunst? (Design and Test of Digital Chips: Science, Technology or Art). VIP paper. A&A, TTU press, No. 2, 2005, pp. 5-9.
  5. Jaan Raik. Pooljuhtide tehnoloogia teeviit aastaks 2016 - kiipide tehnoloogia, projekteerimise ja testi tulevikuvisioon (Semiconductor Industry Roadmap until 2016: A Future Vision of Chip Technology, Design and Test). A&A, TTU press, No. 6, 2003, pp. 9-16.
  6. Jaan Raik. Rahvusvaheline süsteem-kiibil teaduskonverents Soomes - Tampere SoC Symposium 2003. A&A, TTU press, No. 6, 2003, p. 56.
  7. Jaan Raik, Priidu Paomets, Gert Jervan, Antti Markus. Test and Diagnostics Software for Digital Integrated Circuits. Baltic Electronics. #3 1996, p. 4.

 

Presentations


 

jaan@pld.ttu.ee 

Last update: September 2003