Seventh IEEE International Workshop on Testing
Three-Dimensional, Chiplet-Based, and Stacked ICs
3D&Chiplet Test
virtual workshop, continuation of the popular 3D-TEST Workshop in conjunction with ITC / Test Week 2020
November 5-6, 2020
Seventh IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits 3D-TEST

The 3DC-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional, chiplet-based, and stacked ICs (3D-SICs), including systems-in-package (SiP), package-on-package (PoP), 3D-SICs based on through-silicon vias (TSVs), micro-bumps, and/or interposers. While these stacked ICs offer many attractive advantages with respect to heterogeneous integration, small form-factor, high bandwidth and performance, and low power dissipation, there are many open issues with respect to testing such products.

The 3DC-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike. 3DC-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the IEEE Philadelphia Section in concurrence with the Test Technology Technical Council (TTTC).

Further Information:
Erik Jan Marinissen - General Co-Chair
Kapeldreef 75
B-3001 Leuven, Belgium
Tel.: +1 32 16-288755

Yervant Zorian - General Co-Chair
690 East Middlefield Road
Mountain View, CA, USA
Tel.: +1 (650) 584-7120

Bapi Vinnekota - Program Chair
270 Innovation Drive
San Jose, CA, USA
Tel.: +1 (408) 922-1072

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