Java Applet on RT-Level Design
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INTRODUCTION
Applet allows
to solve and illustrate many problems related to RT-level control intensive
digital design together with test. The range of problems includes(but is not
limited to):
- Design of data path
and a microprogram (control path) on the RT-level
- Investigation of tradeoffs
between the speed and hardware cost in the system
- RT level simulation
- Fault simulation and
test coverage evaluation
- Test generation
- Design for testability
and BIST
In this
work different data-path architectures can be chosen - M-automaton, sequential
and parallel IM automata. Each functional unit of the data-path network has
a list of micro-operations, which can be optionally selected for the target
implementation. The units are supported by the RT-level and gate-level models
of the microoperations.
SHORT THEORETICAL
BASICS
System Model
| Each
functional unit F1..F4, MUX, and DMUX has a list of micro-operations
unary or binary. It is supported by an RT-level and gate-level models
of these microoperations. All the microoperations are labeled by a control
signal which activates the microoperation. The description of the data
path functionality in format " control signal: microoperation".
While designing his device (implementing a given algorithm or a function
like multiplication, division etc.) a student can select needed microoperations
for each unit of data path from the whole set of possible predesigned
microoperations. Each microoperation has a gate-level implementation,
and the number of gates determines the cost of the microoperation. By
selecting a set of microoperations for the whole data path the student
will get also the cost of the data path in the number of gates. |
 |
| Each
microoperation has a gate-level implementation, and the number of gates
determines the cost of the microoperation. By selecting a set of microoperations
for the whole data path the student will get also the cost of the data
path in the number of gates. Different architectures can be chosen for
implementation of a given function. Students can compare them and find
the tradeoffs: |
- M-automaton (F1 and
F3 are selected to be transparent, F4 is disabled, all microoperations are
selected only from F2). In this case it is possible to carry out a single
microoperation in one clock cycle, the speed is low, but the cost of HW
is saved.
-
Sequential
IM-automaton (F1, F2, F3 are enabled, F4 is disabled). In this case the
system can carry out maximum 3 microoperations during a single clock cycle
if the algorithm gives such a possibility. For example, in division F1 is
used for inversion to allow subtraction by the adder in F2, and F3 can be
used for shifting of data.
-
Parallel
IM-automaton (all blocks are selected). In this case the system can carry
out maximum 4
microoperations during a single clock cycle if the algorithm allows to.
For instance, while the three
functional units described above perform division, F4 can count clock cycles.
For every chosen architecture, the system calculates the cost of HW. The
speed (the number of clock cycles the
microprogram needs) can be measured by simulation.
Fault simulation
Fault simulation is
carried out at the gate level by using Structural BDD model. Faults for
the given block are inserted into BDDs. The simulation process is controlled
by the data in microprogram table. The target of the fault simulation (a
unit, and a microoperation in the unit) are selected by a student and then
highlighted. The fault simulation data is reported in the Fault Coverage
Table:
Functional Test
It is the cheapest test
technique to be studied. It does not require designing special test programs
and embedding of special test structures into the system. The same unmodified
microprogram and data path configuration are used instead. The required
level of fault coverage must be achieved then by only a smart selection
of input data. The sole checkpoint allowed for catching the fault is the
data path primary output. Moreover, it only can be observed at the time
when the microprogram outputs the final result.
Built-in
Self-Test
| The deterministic
testing via primary inputs/outputs is one of the most efficient ways of
testing. However, it does not provide access to internal signals of the
system under test. This problem is addressed by various DFT and BIST solutions.
Usually it is a scan-path with a random test pattern generator (TPG) and
one or more signature analyzers (SA). In scan-path technology the inputs
and the outputs of the combinational blocks in datapath are directly accessible
by TPGs, SAs or TPG/SA (combined TPG and SA). Two modes may be implemented:
BILBO (Built-In Logic Block Observer) mode based on using TPG and SA,
or CSTP (Circular Self-Test Path) mode based on using combined TPG/SA
scan-path register. Both modes can be implemented in two ways: different
settings for each combinational circuit to be tested, or the same setting
for all circuits. The aim of a student`s work is to find best settings.
For setting the polynomial, the initial state of the TPG, and the number
of clocks to be used for test generation, there is a special subpanel.
Again, the targets for testing are microoperations in blocks F1... F4.
Random test patterns generated by the TPG are saved, then fault simulated,
and finally the fault coverage is displayed. |
Scan-path
design |
Logic BIST
It is common that in
the Logic BIST (L-BIST) method the TPG and SA functions must be separated
and implemented in different registers. On the contrary, in Circular BIST
(C-BIST) both TPG and SA are situated in the same register. The latter approach,
being cheaper, usually does not provide a test of the same quality level as
the former one.
Functional BIST
This idea has very much
in common to Functional Testing. The only difference between the two concepts
is that in the former one there is possibility to insert SAs at any arbitrary
point within the data path. In this way, the observability of the system is
increased, since each such SA is capable of collecting data at each clock
by compressing it into an observable signature.
EXERCISES
APPLET
MANUAL
LIST
OF PUBLICATIONS:
WARNING:
This page contains links to PDF files of articles that may be covered by copyright.
You may browse the articles at your convenience. (in the same spirit as you
may read a journal or a proceeding article in a public library). Retrieving,
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law. We recommend that the user abides international law in accessing this
directory.
- A.
Jutman, M. Kruus, A. Sudnitson, and R.Ubar, “Distance-Learning Tools
for Digital Design and Test Issues,” in Proc. 29th International Conference
and Scientific Discussion Club “Information Technologies in Science,
Education, Telecommunications, Business” (IT+SE’2002), Yalta-Gurzuf,
Ukraine, May 20-30, 2002, pp. 269-272
- S.
Devadze, A. Jutman, A. Sudnitson, R. Ubar, “Web-based training system
for teaching basics of RT-level Digital Design, Test, and Design for Test,”
in Proc. of 9th International Conference on Mixed Design of Integrated Circuits
and Systems (MIXDES 2002), Wroclaw, Poland, June 20-22, 2002, pp. 699-704
- S.
Devadze, A. Jutman, M. Kruus, A. Sudnitson, and R.Ubar, “Web Based
Tools for Synthesis and Testing of Digital Devices”, in Proc. International
Conference on Computer Systems and Technologies (CompSysTech’2002),
Sofia, Bulgaria, June 20-21, 2002, pp. I.91-I.96. (ISBN 954-9641-28-7)
- S.
Devadze, A. Jutman, A. Sudnitson, R. Ubar, H-D. Wuttke, “Java Technology
Based Training System for Teaching Digital Design and Test,” in Proc.
of 8th Baltic Electronics Conference (BEC 2002), Tallinn, Estonia, October
6-9, 2002, pp. 283-286
- S.
Devadze, A. Jutman, A. Sudnitson, R. Ubar, H-D. Wuttke, “Teaching
Digital RT-Level Self-Test using a Java Applet,” 20th IEEE Conference
NORCHIP’2002, Copenhagen, Denmark, November 11-12, 2002, pp.322-328
- A.
Jutman, A. Sudnitson, R. Ubar, “Digital Design Learning System Based
on Java Applets”, in Proc. 4th Annual Conference of the LTSN Centre
for Information and Computer Sciences, NUI Galway, Ireland, August 26-28,
2003, pp.183-187
Last update:
28 July, 2004
