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EXERCISES ON RT-LEVEL DESIGN APPLET
Objectives
Learn to develop different algorithms on RT-level. To explore and compare different methods of testing (such as Functional Test, Deterministic Test, Functional-, Logical- Circular BISTs). Learn to select good operands and good configurations of LFSR, in order to achieve the target fault coverage (FC).
Introduction
Advances in the areas of deep-submicron electron technology and design automation tools are enabling engineers to design larger and more complex integrated circuits, and driving them toward new System on a Chip (SOC) design methodologies. SOC is seen as a major new technology and the future direction for the semiconductor industry.
The more complex electronics systems are getting, the more important will be the problems of testing and design for testability. The cost of test is becoming the major component of the manufacturing cost of a new product. Today, design and test are no longer separate issues. The emphasis on the quality of the shipped products, coupled with the growing complexity of systems design, require testing issues to be considered early in the design process.
Design for Testability (DFT) is rapidly becoming one of the key considerations in today's SOC designs. Moving towards multi-million gate SOCs makes embedded testing strategies via Built-In Self-Test (BIST) architectures mandatory.
Work description
Suppose we have to design and test a digital device that implements a certain algorithm. Therefore, for that purpose we need to develop the algorithm, accordingly to available resources, configure the datapath, design the controller, verify and validate it and find the best way in which we can test our device. In this work we are going to use the "RT-level digital design and test" applet.
First of all our task is to develop the algorithm (microprogram) on a given RT system model, which consists of a several functional units (F1…Fn). Each unit, which is the part of the datapath, contains a number of microoperations (functions: unary and binary), which are activated by corresponding control signals. So, we have a possibility to select one or more microoperations for each functional unit when develop our algorithm. During algorithm implementation we can consider hardware cost or timing requirements by configuring the datapath in an appropriate way. Each microoperation has a gate-level implementation, and the number of gates determines its cost. The speed of the algorithm is measured by the simulation time (a number of clock cycles). After algorithm implementation, we need to make sure that it works properly. For that purpose, we use a panel Test, introducing one or more group of operands. According to the simulation data, which is stored in Simulation Results subpanel we can provide the validation and verification of the implemented algorithm.
After we have finished with algorithm development and validation we need to test the device. To do so, we are going to try different testing techniques (such as Functional testing, Deterministic testing, several BIST methods (BILBO, CSTP, Functional BIST)) and to find the appropriate one, by achieving the target fault coverage (FC).
The first testing method we will try is Functional testing mode. This testing method does not require designing special test programs and embedding of special test structures into the system, therefore it is the cheapest testing technique. Using this method of testing we can achieve the target FC only by a smart selection of operands (test vectors), which are introduced on the subpanel Test. The sole checkpoint allowed for catching the fault in the datapath primary output. Moreover, it only can be observed at the time when the microprogram outputs the final result.
The second testing technique is Deterministic test. This mode is aimed at a gate-level test generation and fault simulation for each selected FU separately. In order to simplify the generation of gate-level test vectors, the gate-level schematic of currently selected FU is displayed. In this case we can select a target fault and generate a test vector. The simulation results are provided in the fault table at the Local Test Panel. For each vector the fault coverage (FC (vec)) is calculated and the information on tested nodes is given. The cumulative fault coverage (FC) is also shown for each simulation step.
Besides Functional and Deterministic testing techniques we will deal with several BIST architectures: such as Logic BIST (BILBO), Circular BIST (CSTP) and Functional BIST. Depending on the chosen BIST method some of them can perform functions of TPG, SA or TPG/SA. If we use the Logic BIST (BILBO) method, the TPG and SA functions must be separated and located in different registers. On the contrary, in Circular BIST (CSTP) both TPG and SA are situated in the same register. In the both modes it is possible to configure the TPG on-line from the interactive graphical panel.
There is another BIST mode, called Functional BIST. This mode has very much in common to Functional Testing. The only difference between the two modes is that in the former one there is possibility to insert SAs at any arbitrary point within the datapath. In this way we increase the observability of the system, since each such SA is capable of collecting data at each clock compressing it into an observable signature.
Load
applet here
Steps
1. You should design different variants of the same given algorithm meeting various constraints. There are two constraints:
Both algorithms should be designed.
2. Perform the validation/verification of the developed algorithms. Evaluate the speed of each algorithm by finding the operands that produce the maximum clock cycles during simulation.
3. Using the Functional Test Mode, you need to select up to 10 groups of operands, which will play the role of test vectors. The operands should be selected so, that the fault coverage (FC) would have been as high as possible. The FC should grow with every selected test vector. If, at some vector it does not grow, the corresponding group of operands should be replaced.
4. Using the Deterministic Test mode, estimate the maximum possible FC for each selected microoperation unit. You should generate test vectors to achieve that maximum FC. Advanced exercise: take the operands from the Deterministic Test mode: a) minimise the number of test vectors at the same FC level, b) improve the FC in Functional Test mode (Step 3)
5. Using the Functional BIST, you should improve the efficiency of Functional Test by introducing a minimal number of additional test points (max. 5 points). In order to increase FC you can change or remove input vectors (operands), if it is necessary. Especially, those ones should be removed, which became useless (FC does not grow).
6. Using the Logic BIST, you should select a good LFSR configuration in order to achieve target (maximum) FC. Try at least 10 different configurations and select the best one. For that purpose you can play with random seeds and polynomials. If the target FC has not been achieved, you can use the primitive polynomials together with proper selection of the seeds based on data from the Deterministic Test mode (Step 4). Advanced exercise: you should find such LFSR configuration, which gives 100% FC for logical gates (AND, OR, NOR, NAND) but requires 3 clock cycles only.
7. Using the Circular BIST, you should repeat step 6. However, note that the difference is in the LFSR configuration, there is a single LFSR for both TPG and SA.
8. Compare the efficiency of all the investigated techniques of testing. Which one is better? Why?
Steps
1. Suppose we have to develop digital device that implements the algorithm (A+B)/2, which calculates the average number of A and B. That algorithm should be implemented on a given RT system model, which is shown in Figure 1 below. For that purpose, we need to define the datapath in an appropriate way, by clicking on highlighted functional blocks and selecting the necessary ones. In the same way, status signals from datapath to control part can be defined. The Microprogram tab-panel helps to define the control part. Clicking right mouse button on specified cells and then selecting value from a popup menu can change all values in some row of a microprogram (including Address, Next State, control signals and conditions). Depends on the number and kind of functional units and microoperations used in the microprogramm the hardware cost is calculated.
Figure 1. The RT-level system model schematic view
We have to develop two
algorithms considering two different constraints:
According to these constraints two algorithms (microprograms) were developed, using different number of functional blocks that cause the difference in the cost of the device. Two functional blocks (F2-binary, F3-unary) with adder and shift (right0) microoperations respectively were used while developing the first algorithm, the hardware cost is 83. In order to decrease the cost of the second one only one functional block F3 was used with adder and shift (right0) microoperations respectively, the hardware cost is 73. The difference between those two algorithms is that in the first one both microoperations are executed sequentially during one clock cycle, whereas in the second one execution takes two clock cycles one for adder microoperation and another for shift right microoperation. The developed microprograms are shown below in table 1 and table 2 respectively.
Table 1. Microprogram for the high cost algorithm
Table 2. Microprogram for the low cost algorithm
2. Introducing the same set of input operands on the panel Test we can perform the validation and verification of both developed algorithms, evaluate the speed and compare them by finding which one is better. The input operands from the Test panel are shown in table 3.
Table 3. Test panel
The simulation data for the both algorithms is stored in the Simulation Results tables presented in tables 4 and 5 shown below.
Table 4. Simulation results of the high- speed algorithm
Table 5. Simulation results of the low cost algorithm
In both cases, the simulation results are the same and the work of the developed algorithms is correct. Evaluating the speed of algorithms we can say, that in case with high cost algorithm the simulation takes 4 clock cycles, whereas in the case with low cost algorithm it takes 5 clock cycles. Further to deal with testing we are going to use high- speed algorithm.
3. To deal with Functional test we need to select from the main menu Functional testing mode. In this mode we should find up to 10 input operands, which give the highest FC for each selected microoperation unit. Each microoperation has a maximum FC, for example the maximum FC that we can achieve in case of adder is 100% (see the related theory http://www.pld.ttu.ee/diagnostika/theory/), but the maximum FC in case of shift is less than 100%. From the Figure 2 shown below we can see that the stuck-at 0 on y3 is impossible to test, since we cannot drive the line to logic 1 in order to sensitize this fault. So, the total maximum FC for the shift microoperation is 7/8 *100%=87,50%.
Figure 2. Schematic view of the shift microoperation
We have made many experiments, in order to find the best operands that produce the target FC for adder and shift microoperations. The 10 operands are presented in the table 6 below.
Table 6. Fault coverage table for Functional test
The maximum FC was achieved in case of functional block F3 (shift right microoperation) is 87,50%, but 10 operands it is not enough to get the target FC for the functional block F2 (adder microoperation). The maximum FC achieved in case with adder is 89,62%. The total FC achieved by functional test for the whole device is 89,55%. Another reason for low fault coverage in case of adder is the shifter, which is not totally transparent.
4. Using deterministic
test we are aimed to achieve the maximum FC for each selected microoperation
unit. So we have to generate test vectors for functional blocks F2 and F3
with adder and shift right microoperations respectively. In order to simplify
the generation of test vectors we can use the gate-level schematic view
of selected functional blocks. The shift microoperation schematic view is
presented above in Figure 2. The adder schematic view you can see in Figure
3 below:
Figure 3. Schematic view of adder microoperation
In table 7 presented below introduced 8 test vectors generated for achieving the 100 % FC for adder microoperation in case with deterministic test. As we can see from the table 7 the fault coverage in column "FC" is growing with each additional test vector.
Table 7. Fault coverage for adder microoperation
To test the shift microoperation we have to drive all the lines with 0 and 1 logic values, for that purpose we need to generate only two test vectors. The maximum FC (87,50%) for the shift microoperation was achieved using test vectors presented in the table 8 below.
Table 8. Fault coverage for shift microoperation
5. Using Functional
BIST we should improve the efficiency of functional test. The same input
operands were used in Functional BIST mode and only one observation point
was added. Since the shift is not totally transparent the observation point
between F2 and F3 functional blocks will help to better test the adder microoperation.
The view of the observation points allocation is shown in Figure 4 below.
Figure 4. Functional BIST schematic view
Even using the additional observation points it is not always the case of achieving the maximum FC. From the table 9 we can see that the FC was increased from 89,62% to 98,11% and the total coverage was increased to 97,73%. We are not going to put additional observation points in order to improve the efficiency of testing shift microoperation because the maximum FC was already achieved in Functional test.
Table 9. Fault coverage table for Functional BIST
There is possibility to improve the efficiency of Functional BIST taking operands from the deterministic test mode and using them in order to achieve the maximum FC for adder microoperation. From the table 10 it is seen that the maximum FC in case of adder was increased to 100%.
Table 10. Fault coverage table for the Functional BIST
6. In Logical BIST mode we have to find a good LFSR configuration in order to achieve the maximum. In case of Logical BIST the testing is provided for each microoperation separately (in present example the adder is going to be tested). The LFSR can be configured in the special applet window (Figure 5), here we define the polynomials and initial states of the generator (TPG) or analyzer (SA).
In our example we use the primitive polynomial x4+x+1 (the register length is 4 bits). It is enough for the test count to be 15, because all other vectors will be generated repeatedly.
Figure 5. LFSR configuration window
We have made 10 experiments and registered the results, which we give in table 11. The column "FC" defines the total fault coverage for all generated configurations, whereas the column "FC (vec)" defines the fault coverage for every particular configuration.
Table 11. Fault coverage for Logical BIST
The testing with Logical BIST was shown that is always possible to achieve the 100% FC even for hard testable microoperations, in our case it was adder microoperation. From the table 11 the best LFSR configuration (Test Nr. 10) was chosen that gives 100% FC, and simulated separately with showing intermediate results, which are presented in table 12 below. In that case we can achieve the 100% FC decreasing the test count to 13.
Table 12. The best LFSR configuration for Logical BIST
In your work you have to simulate all the best configurations and finally select that one which achieves the highest fault coverage at the smallest test length.
In order to test different microoperations the special test programs are used in the applet (Test program panel). These programs define the TPG and SA allocation in the datapath and they are specific for every microoperation. In our example the default test program for adder is presented in table 13 below.
Table 13. Default test program
As an advanced exercise you can modify these programs in order to test several microoperations simultaneously, as it is shown in table 14. In our example, we add the shift microoperation to default test program, in order to test these microoperations simultaneously.
Table 14. Modified test program
The results that we get using modified test program in case of Logical BIST are presented in Global Test panel, which is shown in table 15. In our case, it probably makes no sense since the shift is not transparent for some of the faults and the maximum FC for adder was not achieved, even with modifying default test program.
Table 15. Global Test panel
7. Testing with Circular BIST is very similar to the Logical BIST testing that was introduced in the previous step. This mode has the same aim of selecting the best LFSR configuration, in order to achieve the maximum FC for selected microoperation unit. We have made 10 experiments with different LFSR configurations and give the results in table 16. Analyzing these results we can say that it is not always the case that we achieve the target FC during 10 clock cycles in case with Circular BIST.
Table 16. Fault coverage for Circular BIST
8. Comparing the investigated testing techniques taking the FC and test length as the measure, we can say that on the one hand we improved the efficiency of Functional test using the additional observation points in Functional BIST. On the other hand testing microoperations on logical level with deterministic test we had created the test using which we improved the efficiency of Functional BIST. It is easier to achieve the maximum possible FC for adder and shift microoperations using Logical BIST whether using Circular BIST. In order to test the adder and shift microoperations simultaneously we used the advanced Logical BIST with modified test program. In conclusion, we can say that it is always possible to choose the appropriate testing technique for the device to be tested.
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Last update: 28 July, 2004