The prediagnostic tool (prediag) takes a set of test vectors, applies it to the specification and the implementation of a design and observing the difference in output responses, makes a decision about all the gates in the circuit. Some of gates are sent to the set of correct ones and some are sent to the set of suspected erroneous gates.The information is saved in a report file <design>.rep and also printed to the screen (some comments are given in between of two * (stars):

prompt> prediag c17	*give the name of the design without extension*
Diagnostic Tool for Single Gate Design Errors Reading paths... OK Reading gate names and types... OK   Reading original design... OK Reading test patterns file c17.tst... OK   Reading specification file... OK   Analyzing... OK Time, used by process: 0.000000
Suspected faulty nodes: Format: node name [suspected value]; ... x3 [0];  x4 [D];  g2>inp1 [D];  g3>inp2 [1];  x5 [0]; g4>inp1 [D];	*here we call a node an internal point in a circuit* *actually a node is a certain vertex of a BDD* *this info tells that stuck-at 0 is suspected at* *inputs x3 and x5, s-a 1 suspected at an input of g3,* *and both s-a faults at inputs of g2 and g4, and input x4*
Suspected faulty gates: Format: gate name [suspected value]; ... g2>out [D];  g4>out [1];	*suspected gates are g2 and g4*

The report file c17.rep is also updated and looks as follows:

prompt> more c17.rep
Report File for the Lab Work on Design Error Diagnosis Encrypted name of the modified gate is Y{ABD7`*H{{M\LTS%Hy5)flYyj3S*

AUTOMATIC DIAGNOSIS STEP: Table of input patterns Vector            Inputs   N     x5      x4      x3      x2      x1   01     1        1        1        1        1   02     0        0        0        0        1   03     1        0        1        0        0   04     1        1        0        1        1   05     0        0        0        1        0   Suspected faulty nodes: Format: node name [suspected value]; ... x3 [0];  x4 [D];  g2>inp1 [D];  g3>inp2 [1];  x5 [0]; g4>inp1 [D];   Suspected faulty gates: Format: gate name [suspected value]; ... g2>out [D];  g4>out [1];

*the test used by the prediag is also saved here*         *and the diagnostic data is here*

Last update: 28 July, 2004