| options: | |
| -paths | Preserve information about gate-level signal paths. |
| -spec | Create a specification (insert a design error). |
| -read_iscas89 |
Read
ISCAS'89 format (no library file required!).
|
| -gate_level |
Generate
gate-level SSBDD model (default: macro-level SSBDD model).
|
| -tool <application> |
Options
for 'application' are orcad and cadence.
|
| -gnd <ground> | Specify the ground net name |
| -vdd <voltage> | Specify the VDD net name |
| -clock <pinName> | Specify the clock net name |
| -lib_cell | Generate TT library format output |
| -iscas85 | Generate ISCAS'85 output (do not use with -read_iscas89 option!). |
| -iscas89 | Generate ISCAS'89 output (do not use with -read_iscas89 option!). |
| -general | Generate general (high-level) DD-model |
Error Messages and Warnings
The netlist interface displays error messages and warnings about possible failures while parsing the EDIF netlist file. Line numbers of the input netlist file where errors occurred are provided. Pay attention to ALL of the displayed errors and warnings if the program terminates abnormally!
Note that some of the warnings should be ignored, however. For example, one of the most common warnings during reading a hierarchical design is as follows:
|
This warning shows that there exists a cell named COMPONENT_1 in the EDIF description. It either means that COMPONENT_1 is a block in the hierarchy, or it is a cell, which is not specified in the technology library. In the first case, the warning should be ignored. In the latter case, EDIF parsing fails due to an incompletely specified technology library and the cell COMPONENT_1 should be included to the library.
 |
 |
Last update: 28 July, 2004