The use of
TT tools with default options usually implies that only a design name is given
to a tool (for exapmle: "generate
c17", where "generate"
is the name of the tool and "c17" is the name of the design). Here is the log
of using the deterministic ATPG (the
comments are given in between of two * (stars):
prompt> generate c17 | *give the name of the design to the deterministic ATPG* |
Deterministic
Test Pattern Generator
Reading SSBDD-model file c17.agm... OK Allocating test
patterns... OK |
|
Tested 22 |
*the number of covered
faults* |
Fault
coverage: 100.000000 Fault efficiency: 100.000000 |
*(tested
/ total) x 100%* *(tested / (total - untestable)) x 100%* |
5 Vectors Writing test patterns file c17.tst... OK |
The deterministic ATPG shows two types of coverages as the result of the fault simulaton. The first one (fault coverage) is calculated without taking the amount of theoretically untestable faults into account. The second one (fault efficiency) is calculated after the untestable faults have been subtracted from the total fault number. When the fault coverage achieves 100% the fault efficiency is always achieving 100%. However, the fault efficiency can be 100% while the fault coverage is lower than 100%. This means that some untestable faults exist in the circuit, i.e. such faults for which it is proven that there are no such test vectors that are capable to cover these faults. So, as soon the fault efficiency achieves 100%, a better test cannot be obtained any more. Otherwise the options -backtracks and -vector_limit can be applied in hope to increase the fault coverage. It is not possible to decrase the test length (leaving the coverage the same) playing with these options. The test length can only be shorten for bigger circuits using the test set optimization tool.