CURRICULUM VITAE

 

1. ISIKLIKUD ANDMED
 

Nimi:

 Raimund-Johannes Ubar

Akadeemiline tiitel: 

 tehnikadoktor

Töökoht:


 arvutitehnika instituudi professor, 
 Tallinna Tehnikaülikool

Töökoha aadress:


 Raja tee 15, Tallinn, 12618, Estonia
 Tel.: (372) 620 2252
 Fax: (372) 620 2253
 E-mail: raiub@pld.ttu.ee

2. ANDMED HARIDUSE JA TEADUSLIKE KUTSETE KOHTA

1988  Professor (TTÜ, Moskva-VAK)
1987  Tehnikadoktor (Riia Arvutustehnika instituut, Moskva-VAK)
1978  Dotsent (TTÜ, Moskva-VAK)
1971  Tehnikakandidaat (Moskva Baumani nim. Kõrgem Tehnikakool, VAK)
1968-1971 Aspirantuur Moskva Baumani nim. Kõrgemas Tehnikakoolis
1960-1966 Tallinna Polütehniline instituut
1949-1960 Tallinna 22. Keskkool  (Jakob Westholmi Gümnaasium)

3. AKADEEMILIS - PEDAGOOGILINE TEGEVUS

1992-   Arvutitehnika instituudi professor  TTÜ-s

2003 - 05  Eesti Teaduste Akadeemia uurija-professor

1993 - 97  Elektroonika kompetentsuskeskuse juhataja  TTÜs
1987 - 92  Arvutitehnika kateedri juhataja TTÜ-s
1978 - 87  Dotsent  TTÜ-s
1971 - 78  Vanemõpetaja TTÜ-s
1971 - 71  Assistent  TTÜ-s

1968 - 71  Nooremteadur Moskva Baumani Tehnikaülikoolis (Venemaa)

4. TOOTMISALANE TEGEVUS TÖÖSTUSES

1965 - 1968  Insener, vaneminsener, grupijuht tehase “Punane RET”  Elektroonika Konstrueerimisbüroos

5. ERIALANE TÄIENDAMINE VÄLISMAAL

2003 - 05  Külalisprofessor Jönköpingi Ülikoolis (Rootsi) 2-3 kuud aastas

2002 - 05 Darmstadti Tehnikaülikool (Saksamaa) 2-3 nädalat aastas

2000 Linköpingi Ülikool (Rootsi) 3 kuud

1999 Grenoble’i Joseph Fourier Ülikoolis (Prantsusmaa) 2 kuud

1998 Grenoble’i Polütehniline Instituut (Prantsusmaa) 2 kuud 
1998 Külalisprofessor Grenoble’i Joseph Fourier Ülikoolis (Prantsusmaa) 4 kuud
1997 Fraunhofer’i Integraalskeemide Instituut (Dresden, Saksamaa) 3 kuud
1996 Torino Polütehniline Instituut (Itaalia) 2 kuud
1996 Michigani Ülikool (USA) 1 kuu
1995 Grenoblei’i Polütehniline Instituut (Prantsusmaa) 1,5 kuud
1994 Grenoble’i Polütehniline Instituut (Prantsusmaa) 2 kuud
1993 Darmstadti Tehnikaülikool (Saksamaa) 2 kuud
1992 Grenoble’i Polütehniline Instituut (Prantsusmaa) 4 kuud
1991 Linköpingi Ülikool (Rootsi) 2 kuud
1990 Linköpingi Ülikool (Rootsi) 1 kuu 

1988 Barkhauseni õppetool Dresdeni Tehnikaülikoolis (Saksamaa) 4 kuud

1983 Külalisdotsent Wismari Kõrgemas Tehnikakoolis (Saksamaa) 3 kuud
1975-76  Dresdeni Tehnikaülikool (Ida-Saksamaa) 10 kuud

6. LÄBIVIIDUD KURSUSI VÄLISMAAL

2006  Loengukursus “Digitaalsüsteemide diagnostika ” Ilmenau Tehnikaülikoolis (Saksamaa) 8 t

2003-2005 Loengukursus “Disain ja Test” Jönköpingi Ülikoolis (Rootsi) 36 tundi aastas

2002-2006 Loengukursus “Digitaalsüsteemide testimine” Darmstadti Tehnikaülikoolis (Saksamaa) 36 t /a

2003-2005 Lühikursused teemal “Digitaalsüsteemide diagnostika” 10 Euroopa riigis – 22 loengut á 4t

2001 Loengukursus “Disain ja Test” Jönköpingi Ülikoolis (Rootsi) 36 t

1998 Loengukursus “Diagnostika” firmas Ericsson Telecom AB (Stockholm, Rootsi) 4 tundi
1995 Loengukursus “Diagnostika” Helsinki Tehnikaülikoolis (Soome) 16 t
1995 Loengukursus “Digitaalsüsteemide diagnostika” Michigani Ülikoolis (USA) 16 t
1994 Loengukursus “Veakindlad digitaalsüsteemid” Darmstadti Tehnikaülikoolis (Saksamaa) 12 t
1991 Loengukursus “Digit.süsteemide diagnostika” Linköpingi Ülikoolis (Rootsi) 16 t
1991 Loengukursus “Testide süntees ja analüüs arvutiskeemides” Riia PI ja tehas VEF (Läti)  32 t
1988 Loengukursus  “Digitaalsüsteemide diagnostika” Dresdeni Tehnikaülikoolis (Saksamaa) 16 t
1988 Loengukursus “Digitaalsüsteemide diagnostika” (Chemnitzi Tehnikaülikoolis (Saksamaa) 16 t
1976 - 1988 Loengukursused Ilmenau Tehnikaülikoolis (Saksamaa) teemal “Digitaalsüsteemide testimine ja diagnostika” (aastatel 1976, 1977, 1979, 1980, 1983, 1986 ja 1988 mahus 12 tundi)

Loenguid või lühemaid loengukursusi veel 25-30 ülikoolis või teaduslikus uurimisasutuses USA-s, Soomes, Rootsis, Norras, Taanis, Saksamaal, Prantsusmaal, Itaalias, Poolas, Ungaris, T¹ehhis, Slovakkias, Bulgaarias, Venemaal ja teistes maades.

7. AKADEEMILINE SPETSIALISEERUMINE

a) õppetöö osas
Bakalaureusekursused:
- Digitaalsüsteemide diagnostika
- Digitaalsüsteemide disain ja test
- Veakindlad digitaalsüsteemid 
Magistrikursused:
- Sissejuhatus Boole’i diferentsiaalalgebrasse
- Otsustusdiagrammid ja digitaalsüsteemide diagnostika”
- Testide süntees digitaalsüsteemides
- Testide analüüs digitaalsüsteemides
- Testitavuse parandamine digitaalsüsteemides
Oma ülikoolikarjääri jooksul olen lugenud veel kursusi programmeerimisest, elektroonikast, analoog- ja digitaalarvutitest, automaatide teooriast, arvutite aritmeetika ja loogika alustest, arvutite hooldusest, automaatikavahendite konstrueerimisest, digitaalsüsteemide kaasaegsetest projekteerimismeetoditest jms.
b) teadustöö osas
- digitaalsüsteemide testimine ja rikete diagnostika
- intelligentsete testsüsteemide arhitektuurid
- Boole’i diferentsiaalalgebra rakendused loogikaskeemide diagnostikas
- otsustusdiagrammid ja nende rakendamine digitaalsüsteemide diagnostikas
- digitaaltehnika diagnostika tarkvara projekteerimine
- veakindlad arvutisüsteemid
- digitaalsüsteemide diagnostiline modelleerimine
c) teaduslik juhendamine 40 kaitstud teaduskraadi
- juhendatud tehnikakandidaadid (11): E.Orasson (2007), E.Ivask (2006), A.Jutman (2004), M.Brik (2002), J.Raik (2001), J.Dushina (1999), T.Evartson (1987), A.Voolaine (1986), M.Pall (1986), M.Plakk (1984), P.Kitsnik (1981)
- juhendatud magistrid (29): S.Kostin (2007), A.Kurbatov, J.Sudbrock, T.Schchenova (2005), D.Zhukov, J.Grüning, J.Tünni, M.Jenihhin, V.Govind, J.Smahtina, N.Mazurova, V.Vislogubov (2004), H.Kruus (2003), E.Orasson, R.Raidma (2002), M.Aarna, J.Heinlaid, L.Raun (2001), A.Jutman (1999), G.Jervan, E.Ivask, P.Paomets (1998), J.Raik (1997), M.Brik (1994), A.Buldas, H.Krupnova, S.Storozhev, J.Dushina, V.Zaugarov (1993)
 

8. TEADUSPROJEKTID

Euroopa Ühenduse projektid:

  1. V Framework IST 033709 Verification and validation of Embedded System Design workbench – VERTIGO (2006 -2008)
  2. V Framework IST-2001-37592 Establishment of the Virtual Centre of  Excellence for IST RTD in Estonia -eVIKINGS II (2002 - 2005)
  3. V Framework IST-2000-30193 Research and Training Actionfor System on Chip Design - REASON (2002 - 2005)
  4. European Thematic Network 10063-CP-1-2000-1-PT-ERASMUS-ETNE Thematic Harmonisation in Electrical and Information EngineeRing in Europe – THEIERE (2002-2005)
  5. INCO JEP 977133 Microelectronics Virtual Laboratory for Cooperation in Research and Knowledge Transfer - VILAB (1998-2001)
  6. INCO-COPERNICUS JEP 9601/70 Promotion of System Design Training and Information Centers in CCE/NIS - SYTIC (1996-1998)
  7. COPERNICUS JEP 9624 Functional Test Generation  and  Diagnosis – FUTEG (1994-1997)
  8. PECO JEP 7668 East European Microelectronics Cooperation Network of Support and Competence Centres - EEMCN (1993-1996)
  9. ESPRIT III BRA-6575 Advanced test generation and testable design methodology for sequential circuits - ATSEC (1994-1996)
  10. ESPRIT Action EUROPRACTICE (1995 -)
  11. ESPRIT Action EUROCHIP (1993-1995)
  12. Promotion of the use of professional CAD  software at universities EUROCHIP Action (1993 - 1995)
  13. TEMPUS JEP 4772 "Digital System Design Based on PLD-Technology" (1992-95)

Bilateraalsed rahvusvahelised projektid:

  1. Estonian - Polish Joint Research Project. Analysis and Testing of Physical Defects in Digital Circuits and Systems. Partner: TU Warsaw (2007-2009)
  2. German-Estonian project. MOSCITO-based Test Tool Integration for Resarch and eLearning aided Education. Partner: Fraunhofer Gesellschaft, Institute of Integrated Circuits, Dresden (2004-2006)
  3. Estonian- Polish Joint Research Project. Defect-Oriented Testing of  Digital Systems. Partner: TU Warsaw (2003-2005)
  4. German-Estonian project DILDIS. Distance Learning on Digital Systems. Partner: TU Ilmenau (2002-2006)
  5. German-Estonian project. Functional Built-in Self-Test in Digital Systems. Partners: Fraunhofer Gesellschaft, Institute of Integrated Circuits, Dresden; University Stuttgart (2000-2002).
  6. German-Estonian project DILDIS. Distance Learning on Digital Systems. Partner: TU Ilmenau (1999-2001).
  7. Swedish-Estonian project. Design and Test of Dependable Electronic Systems. Partner: Linköping University (1999-2000).
  8. German-Estonian project. EST-008-96 Automated Test Generation for FPGA based Designs. Partner: Fraunhofer Gesellschaft, Institute of Integrated Circuits, Dresden (1996-1999).
  9. Estonian - Swedish project. Generic VHDL Descriptions for Synthesizing Embedded Test Processors. Partner: Jonköping University (1996-1997).

10.  Digital Encryption Standard Macroblock. Partner: Fincitec OY Finland (1996).

 

Eesti grantid ja projektid:

  1. Töökindlate arvutisüsteemide uurimise tippkeskus (2003-2007).
  2. Sihtfinantseerimise teema: Digitaalsüsteemide disain ja test (2003-2007).
  3. Eesti Teaduste Akadeemia uurija-professuur. Uued digitaaltesti meetodid (2003-2005).
  4. Sihtfinantseerimise teema: Uurimis- ja arendustöö ning rakendused digitaalsüsteemide disainis ja testis (1998-2002).
  5. Baasfinantseerimise teema: Isetestivate süsteemide diagnostilise modelleerimise keskkond (2007)
  6. Baasfinantseerimise teema: Kaasfinantseerimine europrojektile VERTIGO (2006).
  7. ETF Grant 5910. Isetestivad digitaalsüsteemid (2004-2007)
  8. ETF Grant 5649. Digitaalsüsteemide defekt-orienteeritud testimine (2003-2006).
  9. ETF Grant 4003. Disainivigade diagnostika digitaalskeemides ja süsteemides (200-2003).
  10. ETF Grant 3658. Digitaalelektroonika disaini ja testi virtuaalne laboratoorium (1999-2002).
  11. ETF Grant 1850. Digitaalsüsteemide diagnostilise analüüsi hierarhiliste meetodite uurimine ja väljatöötamine (1996-1999).
  12. ETF Grant 2104. Digitaalelektroonika nüüdisaegse projekteerimise ja teadusuuringute eksperimentaalkeskkond (1996-1998).
  13. ETF Grant 1434. TTÜ elektroonika kompetentsuskeskuse infrastruktuur (1993).
  14. ETF Grant 1433. Meetodid ja tarkvara digitaalsüsteemide diagnostikas (1993-1995).
  15. Informaatikafondi grant (leping nr. 227). Andmeturve riistvara projekteerimise ja valmistamise keskkonna välja arendamine (1993-1995).
  16. Innovatsioonifondi grant. Kaasaegse elektroonika, arvutustehnika ja informatsioonitehnika vahendite disaini käivitamine Eestis (1994-1995).
  17. Eesti Valitsuse grant TTÜ Elektroonika Kompetentsuskeskusele. Kaasaegse elektroonikadisaini käivitamine Eestis (1994-1995).

Lepinguline töö Eesti ettevõtetega:

  1. Lepinguline töö. Kontseptsioon ja diagnostikavahendid mikroprotsessorite isetestimiseks – MIKROTEST. Partner: Artec Design. (2001-2003).
  2. Lepinguline töö nr. 6412 “Krüptokiibi prototüübi tehnoloogilise faili projekteerimine” Partner: Küberneetika instituut. (1996).
  3. Lepinguline töö “Krüptokiibi prototüübi testimine ja dokumentatsiooni väljatöötamine”. Partner: Küberneetika instituut. (1996-1997).

9. ORGANISATOORNE TEGUTSEMINE ELUKUTSE ALAL

a) Organisatsiooniline tegevus  ja kuuluvus rahvusvahelises plaanis:

  1. IEEE (USA Elektri- ja Elektroonikainseneride Ühing) – Computer Society Golden Core Member (alates 2006)
  2. Test Technology Technical Committee (TTTC), liige (alates 1998)
  3. European Test Technology Technical Committee (ETTTC), liige (alates 1995)
  4. Nordic Test Forum, liige (alates 2005)
  5. Council of the European Assotiation of Electrical and Information Engineers (EAEEIE), liige (alates 2001)
  6. International Academy of Sciences and Arts, USA (alates 1996)
  7. Baltic Academy of Technological Sciences (asutajaliige, 1992)
  8. Nordic and Baltic Journal of Information and Communication Technologies, Advisory Board – liige (alates 2006)
  9. Journal of Information Technology and Control, Editorial board (alates 2005)
  10. IEEE Education Society (USA), liige (alates 1995)
  11. IEEE Circuits and Systems Society (USA), liige (alates 1995)
  12. IEEE Technical Council on Software Engineering European regional group (alates 1995)
  13. IEEE Computer Society (USA), liige (alates 1994)
  14. Institution of Engineering and Technology (endine IEE), liige (alates 2005)
  15. Assotiation for Computin Mashinery (USA) (liige alates 1996)
  16. Saksamaa Informaatikaühing (GI) (liige alates 1995)
  17. Assotiation EUROPRACTICE (liige alates 1995)
  18. Assotiation EUROCHIP (liige 1993-1995)
  19. 10th IEEE European Test Symposion – General Chair (2005)
  20. IEEE Conference NORCHIP  peakorraldaja – General Chair (1997)
  21. 9th IEEE European Test Symposion – General Vice Chair (2005)
  22. IEEE East-West Design & Test Conferences EWDTW'03, EWDTW'04, EWDTW'05, EWDTW'06, EWDTS'07 – General Vice Chair (alates 2003)
  23. International Conference on Microelectronics, Devices and materials (MIDEM) - General Vice Chair (2007)
  24. IEEE VLSI Test Symposion (VTS) - Eastern Europe Liaison (alates 2007)
  25. IEEE Latin American Test Workshop (LATW) - Eastern Europe Liaison (alates 2007)
  26. IEEE Workshop on Design and Diagnostics of Electronic System (DDECS) – Publicity Chair (alates 2005)
  27. Council of the All-Union Association of Technical Diagnostics (1991-1993)
  28. Kuulumine rahvusvaheliste konverentside juhtkomiteedesse: VTS, EDCC, DDECS, LATW, EWD&TS, NORCHIP, BEC
  29. Kuulumine rahvusvaheliste konverentside programmikomiteedesse: DATE, ISQED, VTS, LATW, EDCC, ETW, ETS, EWDC, ECCTD, DSD, IMCL, DDECS, EUROMICRO, NORCHIP, IWoTA, MIXDES, ITHET, EAEEIE, MIDEM, ECS, AQTR, EWDTW, BEC jt.

 

b) Organisatsiooniline tegevus Eestis väljaspool ülikooli:

  1. Eesti Teaduste Akadeemia tegevliige (alates 1993)
  2. Eesti Presidendi Akadeemilise Nõukogu liige (1993-1996)
  3. Eesti Teadus- ja Arendusnõukogu liige (1993-1997)
  4. Eesti Teadusfondi Nõukogu esimees (1993-1997)
  5. Eesti Teadusfondi Tehnikateaduste ekspertkomisjoni esimees (1993-1997)
  6. Eesti Vabariigi Teaduspreemiate komisjoni liige (1994-1996, 2005- )
  7. Eesti TA Informaatika ja Tehnikateaduste Osakonna büroo liige (alates 1994)
  8. Eesti Teadlaste Liidu Volikogu liige (alates 1991 - 2005)
  9. Eesti Automaatikute seltsi liige (alates 1991)
  10. Eesti Elektroonikaühingu liige (alates 1992)
  11. Eesti Informaatikanôukogu ekspert (alates 1993 -1996 )
  12. Kultuurialase eesti-saksa segakomisjoni liige Haridusministeeriumi juures (alates 1994 - 1997)

c) Organisatsiooniline tegevus ülikoolis:

  1. TTÜ Infotehnoloogiateaduskonna Nõukogu liige (2005-)
  2. TTÜ Nôukogu liige (1987-1995)
  3. TTÜ Konkursikomisjon (1992-1994 esimees, 1994-1996 komisjoni liige)
  4. Elektrotehnika doktorite nôukogu esimees (1992-1995)
  5. TTÜ nôukogu arengukomisjoni liige (1994- 1995)
  6. TTÜ nôukogu teaduskomisjoni liige (1994- 1995)
  7. Automaatika teaduskonna nôukogu liige (1992-1996)
  8. Infotehnika teaduskonna nõukogu liige (1997 - )

 

9. AUTASUD

2006  IEEE Computer Society Golden Core Award

2005  IEEE Computer Society Meritorious Service Award

2003  Harkovi Rahvusliku Raadiotehnika Űlikooli auprofessor

2002  Riiklik autasu: Valgetähe III klassi orden

2001  TTÜ Teenete medal Mente et Manu

1999  Eesti Vabariigi teaduspreemia, Loodusteadused ja tehnika

1997  TTÜ Kuldmärk
1986  Kaks hõbemedalit Üleliiduliselt Rahvamajanduse Näituselt Moskvas

10. TEADUSLIKUD PUBLIKATSIOONID

a) monograafiad, raamatud, õpikud

  1. O.Novak, E.Gramatova, R.Ubar. Handbook of Electronic Testing. CTU Printhouse, Prague, 2005, 400 p.
  2. R.Ubar. Digitaalsüsteemide diagnostika. I. Diagnostiline modelleerimine. Tallinn, TTÜ Kirjastus, 2005, 148 lk.
  3. D. Bochmann and R. Ubar. Fehler in Automaten. VEB  Verlag  Technik, Berlin, 1989,  216 p.
  4. R. Ubar.  Design of Digital Systems for Testability. Tallinn  Technical University, 1988, 68 pp. (in Russian).
  5. R.Ubar. Operational Automata in Digital Computers. Tallinn Technical University, 1987, 96 p. (in Estonian).
  6. P.Kitsnik, T.Lohuaru, R.Ubar. Test Design System for Digital Automata. Tallinn Techn. University, 1984, 58p. (in Russian)
  7. A. Seleznev, B. Dobriza, R. Ubar. Design of Automatic Test Equipments. Mashinostrojenie, Moscow, USSR, 1983, 224 p. (in Russian).
  8. R.Ubar. Diagnosis of Digital Devices. I. Tallinn  Techn.  University, 1980, 114 pp. (in Russian).
  9. R.Ubar. Diagnosis of Digital Devices. II. Tallinn  Techn.  University, 1981, 112 pp. (in Russian).
  10. R.Ubar. Functional blocks in Digital Computers. Tallinn Technical University, 1978, 103p. (in Estonian).

 

b) valitud teaduslikud artiklid

 

1.        R.Ubar, S.Devadze, J.Raik, A.Jutman. Fast Fault Simulation in Digital Circuits with Scan Path. 13th Asia and South Pacific Design Automation Conference – ASP-DAC 2008, Seoul, Korea, Jan. 21-24, 2008, (to appear).

2.       R.Ubar, S.Devadze, M.Jenihhin, J.Raik, G.Jervan, P.Ellervee. Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. 4th IEEE International Symposium on Electronic Design, Test & Applications – DELTA 2008, Hong Kong, January 23-25, 2008 (to appear).

3.        J.Raik, R.Ubar, T.Viilukas, M.Jenihhin. Mixed Hierarchical-Functional Fault Models for Targeting Sequential Cores. Journal of Systems Architecture, 2007 (to appear).

4.        R.Ubar, J.Raik, H.Kruus, H.Lensen, T.Evartson. Diagnostic Modelling of Digital Systems with Binary and High-Level Decision Diagrams. In “Progress in Industrial Mathematics at ECMI 2006”, Series: Mathematics in Industry, Subseries: The European Consortium for Mathematics in Industry , Vol. 12, Bonilla, L.L.; Moscoso, M.; Platero, G.; Vega, J.M. (Eds.), ISBN: 978-3-540-71991-5”, 2007 (available Dec.4, 2007).

5.        P.Ellervee, J.Raik, R.Ubar, K.Tammemäe. FPGA-Based Fault Emulation of Synchronous Sequential Circuits. IEE Proceedings on Computers & Digital Techniques. Vol.1, Issue 2, pp.70-76, March 2007.

6.        R.Ubar, A.Jutman, M.Kruus, E.Orasson, S.Devadze, H.-D.Wuttke. Learning Digital Test and Diagnostics via Internet. International Journal of Emerging Technologies in Learning. International Journal of Online Engineering, Vol.3, No.1, pp.1-9, 2007.

7.        R.Ubar, M.Kruus, T.Rang. Electronics Design and Test. Public Service Review: European Union, Issue 13, 2007, p.52-53.

8.        R.Ubar, S.Devadze, J.Raik, A.Jutman. Ultra Fast Parallel Fault Analysis on Structural BDDs. 12th IEEE European Test Symposium – ETS 2007, Freiburg, Germany, May 20-24, 2007, pp.131-136.

9.        G.Jervan, H.Kruus, E.Orasson, R.Ubar. Hybrid BIST Optimization Using Reseeding and Test Set Compaction. Proc. of 10th IEEE EUROMICRO Conference on Digital System Design - DSD 2007, Lübeck, Germany, August 27 - 31, 2007, pp.596-603.

10.    J.Raik, R.Ubar, A.Krivenko, M.Kruus. Hierarchical Identification of Untestable Faults in Sequential Circuits. Proc. of 10th IEEE EUROMICRO Conference on Digital System Design - DSD 2007, Lübeck, Germany, August 27 - 31, 2007, pp.668-671.

11.    R.Ubar, S.Kostin, J.Raik, T.Evartson, H.Lensen. Fault Diagnosis in Integrated Circuits with BIST. Proc. of 10th IEEE EUROMICRO Conference on Digital System Design - DSD 2007, Lübeck, Germany, August 27 - 31, 2007, pp.604-610.

12.    M.Jenihhin, J.Raik, A.Chepurov, R.Ubar. Assertion Checking with PSL and High-Level Decision Diagrams. Diggest of Papers IEEE 8th Workshop on RTL and High Level Testing - WRTLT'07. Beijing, P.R.China, Oct. 12-13, 2007, pp.105-110.

13.    G.Jervan, Z.Peng, T.Shchenova, R.Ubar. A Hybrid BIST Energy Minimization Technique for SoC Testing. IEE Proceedings on Computers & Digital Techniques, July 2006, Vol. 153, Issue 4, pp.208-216.

14.    T.Bengtsson, A.Jutman, S.Kumar, Z.Peng, R.Ubar. Off-line Testing of Delay Faults in NoC Interconnects. Proceedings of the 9th IEEE EUROMICRO Conference on Digital Systems Design DSD2006, Katvat, Croatia, 2006, pp.677-680.

15.    J.Raik, R.Ubar. T.Viilukas. High-Level Decision Diagram based Fault Models for Targeting FSMs. Proceedings of the 9th IEEE EUROMICRO Conference on Digital Systems Design DSD2006, Katvat, Croatia, 2006, pp.353-358.

16.    G.Jervan, R.Ubar, Z.Peng. Hybrid BIST Methodology for Testing Core-Based Systems. Proc. of the Estonian Academy of Sciences. Engineering, 12 (2/3), pp.300-322.

17.    P.Ellervee, J.Raik, K.Tammemäe, R.Ubar. Environment for FPGA Based Fault Emulation. Proc. of the Estonian Academy of Sciences. Engineering 12 (2/3), pp.323-335.

18.    G.Jervan, P.Eles, Z.Peng, R.Ubar, M.Jenihhin. Test Time Minimization for Hybrid BIST of Core-Based Systems. J. of Computer Science and Technology. Nov. 2006, Vol. 21, No. 6, pp. 907-912.

19.    M.Kruus, R.Ubar. Success Story of the Computer Engineering Department at the Tallinn University of Technology in EU Projects. The Parliament Magazine. No. 234, 13. Nov. 2006, pp.33.

20.    V.Govind, J.Raik, R.Ubar. An External Test Approach for Network-on-Chip Switches. IEEE Asian test Symposium. 2006, Fukuoka, Japan, pp.437-442.

21.    R.Ubar, J.Raik, A.Jutman, P.Ellervee. Digital Electronics Design and Test at Computer Engineering Department of Tallinn University of Technology. The House Magazine. The Parlamentary Weekly, No 1198, Vol.32, Dec.11, 2006, pp.42.

22.    J.Raik, R.Ubar, S.Devadze, A.Jutman. Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. Lecture Notes in Computer Science, Vol. 3463, Springer Verlag, Berlin, Heidelberg, New York 2005, pp. 332-344.

23.    J.Raik, T.Nõmmeots, R.Ubar. A New Testability Calculation Method to Guide RTL Test Generation. Journal of Electronic Testing: Theory and Applications – JETTA. Springer Science + Business Media, Inc. 21, pp.73-84, 2005.

24.    G.Jervan, R.Ubar, Z.Peng, P.Eles. Test Generation: A Hierarchical Approach. In “System-level Test and Validation of Hardware/Software Systems” by M.Sonza Reorda, Z.Peng, M.Violante. Springer Series in Advanced Microelectronics, Vol.17, 2005, pp. 63-77.

25.    G.Jervan, R.Ubar, Z.Peng, P.Eles. An Approach to System Level DFT. In “System-level Test and Validation of Hardware/Software Systems” by M.Sonza Reorda, Z.Peng, M.Violante. Springer Series in Advanced Microelectronics, Vol.17, 2005, pp. 91-118.

26.    A.Matrosova, A.Pleshkov, R.Ubar. Test Generation for Combinational Circuits by Orthogonal Disjunctive Normal Forms and SSBDDs. Avtomatika i Telemekhanika, No. 2, 2005, pp. 158–174 (in Russian).

27.    A.Matrosova, A.Pleshkov, R.Ubar. Construction of the Tests of Combinational Circuit Failures by Analyzing the Orthogonal Disjunctive Normal Forms Represented by the Alternative Graphs. J. of Automation and Remote Control. Publisher: Springer Science & Business Media B.V., 66 (2), 2005, pp. 313-327.

28.    R.Ubar, T.Shchenova, G.Jervan, Z.Peng. Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment. Proc. of 10th IEEE European Test Symposium, May 22-25, 2005, Tallinn, pp.2-7.

29.    J.Raik, R.Ubar, J.Sudbrock, W.Kuzmicz, W.Pleskacz. DOT: New Deterministic Defect-Oriented ATPG Tool. Proc. of 10th IEEE European Test Symposium, May 22-25, 2005, Tallinn, pp.96-101.

30.    A.Jutman, V.Rosin, A.Sudnitson, R.Ubar, H.-D.Wuttke A System for Teaching Basic and Advanced Topics of IEEE 1149.1 Boundary Scan Standard. EAEEIE, June 2005. Best Paper Award.

31.    J.Raik, P.Ellervee, V.Tihhomirov, R.Ubar. Improved Fault Emulation for Synchronous Sequential Circuits. 8th Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.72-78.

32.    J.Sudbrock, J.Raik, R.Ubar, W.Kuzmicz, W.Pleskacz. Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. 8th Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.79-82.

33.    R.Ubar. Decision Diagrams and Digital Test. 41th International Conference on Microelectronics, Devices and Materials – MIDEM 2005, Ribno at Bled, Slovenia, Sept. 14.-16, 2005, pp.15-26. Invited plenary paper.

34.    R.Ubar. Decision Diagrams and Digital Test. Informacije MIDEM-Journal of Microelectronics Electronic Components and Materials, 35(4), 2005, pp.187 - 195.

35.    R.Ubar, M.Jenihhin, G.Jervan, Z.Peng. Hybrid BIST Optimization for Core-Based Systems with Test Pattern Broadcasting. 2nd IEEE Int. Workshop on Electronic Design, Test and Applications – DELTA’04, Perth, Australia, 28-30 January 2004, pp.3-8.

36.    R.Ubar, M.Jenihhin, G.Jervan, Z.Peng. An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture. 5th IEEE Latin-American Test Workshop – LATW 2004. Digest of Papers, Cartagena, Colombia, March 8-10, 2004, pp.98-103.

37.    A.Jutman, R.Ubar, H.-D.Wuttke. Overview of E-Learning Environment for Web-Based Study of Testing and Diagnostics of Digital Systems. 5th European Workshop on Microelectronics Education – EWME 2004, Lausanne, April 15-16, 2004, pp. 173-176.

38.    E. Ivask, J. Raik, R. Ubar, A. Schneider. WEB-Based Environment: Remote Use of Digital Electronics Test Tools. In “Virtual Enterprises and Collaborative Networks”, Kluwer Academic Publishers, 2004, pp. 435-442.

39.    A.Jutman, R.Ubar, H.-D.Wuttke. Overview of E-Learning Environment for Web-Based Study of Testing and Diagnostics of Digital Systems. In “Microelectronics Education” Kluwer Academic Publishers, 2004, pp.253-258.

40.    R.Ubar. Design Error Diagnosis with Resynthesis in Combinational Circuits. Journal of Electronic Testing: Theory and Applications 19, 73-82, 2003. Kluwer Academic Publishers.

41.    R.Ubar, J.Raik. Testing Strategies for Networks on Chip. In “Networks on Chip” by A.Jantsch, H.Tenhunen. Kluwer Academic Publishers, 2003, pp. 131-152.

42.    R.Ubar. Decision Diagrams and Digital Test. Proc. of the 6th International Workshop on Electronics, Control, Measurement and Signals, Liberec, Czechia, June 2-4, 2003, pp.266-273. Invited plenary paper.

43.    A.Jutman, A.Sudnitsõn, R.Ubar. Web-Based Applet for Teaching Boundary Scan standard IEEE 1149.1. Proc. of the 10th Int. Conf. MIXDES 2003, Lodz, June 26-28, 2003, pp.584-589. Best Paper Award.

44.    R.Ubar. Mapping Faults in Hierarchical testing of Digital Systems. Proc. of the Int. Conf. On Computer, Communication and Control technologies – CCCT’03. Orlando, USA, July 31 – August 2, 2003, pp.14-19. Best Paper Award.

45.    V.Hahanov, R.Ubar, S.Hyduke. Back-Traced Deductive-Parallel Fault Simulation for Digital Systems. Proc. of EUROMICRO Symposion on Digital System Design - DSD’2003. Belek-Antalaya, Turkey, September 3-5, 2003, pp. 370-377.

46.    G.Jervan, P.Eles, Z.Peng, R.Ubar, M.Jenihhin. Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. 18th Int. Symposium on Defect and Fault Tolerance in VLSI Systems. Cambridge, MA, USA, November 3-5, 2003.

47.    G.Jervan, P.Eles, Z.Peng, R.Ubar, M.Jenihhin. Test Time Minimization for Hybrid BIST of Core-Based Systems. Asian Test Symposium 2003, Xi’an, China, November 17-19, 2003, pp. 318-323.

48.    V.Hahanov, R.Ubar. First East-West Design and Test Conference. IEEE Design & Test, Nov.-Dec 2003, pp.103.

49.    R.Ubar, E.Rüstern, M.Kruus. EE: Eesti (Estonia) in “Towards the Harmonization of Electrical and Information Engineering Education in Europe”, Lisboa-Nancy 2003, Ed. EAEEIE, 2003, pp.67-74.

50.    R.Ubar, J.Raik, E.Ivask, M.Brik. Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. IEEE Workshop on Electronic Design, Test and Applications – DELTA’02, Christchurch, New Zealand, 29-31 January 2002, pp.86-91.

51.    R.Ubar. Testability Calculation for Digital Circuits with Decision Diagrams. 3rd IEEE Latin-American Test Workshop – LATW’2002, Montevideo, Uruguay, February 10-13, 2002, pp.137-143.

52.    A.Schneider, E.Ivask, P.Miklo¹, J.Raik, K.H.Diener, R.Ubar, T.Cibáková, E.Gramatová. Internet-based Collaborative Test Generation with MOSCITO. IEEE Proc. of  Design Automation and Test in Europe – DATE’02. Paris, March  4-8, 2002, pp. 221-226.

53.    T.Cibáková, M.Fischerová, E.Gramatová, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Test Generation for Combinational Circuits with Real Defects Coverage. Pergamon Press. Journal of Microelectronics Reliability, Vol. 42, 2002, pp.1141-1149.

54.    G.Jervan, H.Kruus, Z.Peng, R.Ubar. About Cost Optimization of Hybrid BIST in Digital Systems. 3rd IEEE Int. Symp. on Quality of Electronic Design, San Jose, California, March 18-20, 2002, pp.273-279.

55.    R.Ubar, J.Raik, E.Ivask, M.Brik. Defect-Oriented Mixed-Level Fault Simulation in Digital Systems. Facta Universitatis (Nis), Ser.: Elec. Energ. Vol.15, No.1, April 2002, pp.123-136.

56.    A.Schneider, K.-H.Diener, G.Elst, E.Ivask, J.Raik, R.Ubar. Internet-Based Testability-Driven Test Generation in the Virtual Environment MOSCITO. Proc. IFIP Conference on IP Based SOC Design, Grenoble, France, October 30-31, 2002, pp.357-362.

57.    R.Ubar. Design Error Diagnosis in Scan-Path Designs. 2nd Latin-American Test Workshop. Cancun, Mexico, February 11-14, 2001, pp. 162-168.

58.    A.Jutman, R.Ubar, Z.Peng. Algorithms for Speeding-Up Timing Simulation of Digital Circuits. DATE, Munich, March 13-16, 2001, pp.460-465.

59.    R.Ubar, W.Kuzmicz, W.Pleskacz, J.Raik. Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. 2nd Int. Symp. on Quality of Electronic Design, San Jose, California, March 26-28, 2001, pp.365-371.

60.    J.Raik, A.Jutman, R.Ubar. Fast Static Compaction of Test Sequences Using Implications and Greedy Search. Digest of European Test Workshop, Stockholm, May 29 – June 1, 20001, pp. 207-210.

61.    T.Hollstein, Z.Peng, R.Ubar, M.Glesner. Challenges for Future System-on-Chip Design. Proceedings of European Conference on Circuit Theory and Design. Part III. Espoo, Finland, August 28-31, 2001, pp.173-176.

62.    R.Ubar, G.Jervan, Z.Peng, E.Orasson, R.Raidma. Fast Test Cost Calculation for Hybrid BIST in Digital Systems. Proc. of EUROMICRO Symposium on Digital Systems Design, Warsaw, September 4-6, 2001, pp.318-325.

63.    R.Ubar, H.-D.Wuttke. The DILDIS-Project – Using Applets for More Demonstrative Lectures in Digital Systems Design and Test. Proceedings of the 31st ASEE/IEEE Frontiers in Education Conference, FIE’2001, Oct. 10-13, 2001, Reno, NV, USA, pp.SIE-2-7.

64.    M.Blyzniuk, I.Kazymyra, W.Kuzmicz, W.A.Pleskacz, J.Raik, R.Ubar. Probabilistic Analysis of CMOS Physical Defects in VLSI Circuits for Test Coverage Improvements. Journal of Microelectronics Reliability. Pergamon Press. Vol  41/12, Dec. 2001, pp 2023-2040.

65.    W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Module Level Defect Simulation in Digital Circuits. Proceedings of the Estonian Academy of Sciences, No 7/4, 2001, pp.253-268.

66.    A.Jutman, R.Ubar. Application of Structurally Synthesized Binary Decision Diagrams for Timing Simulation of Digital Circuits. Proceedings of the Estonian Academy of Sciences, No 7/4, 2001, pp.269-288.

67.    A.Jutman, R.Ubar. Design Error Diagnosis in Digital Circuits with Stuck-at Fault Model. Journal of Microelectronics Reliability. Pergamon Press, Vol. 40, No 2, 2000, pp.307-320.

68.    J.Raik, R.Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. Journal of Electronic Testing: Theory and Applications. Kluwer Academic Publishers. Vol. 16, No. 3, pp. 213-226, 2000.

69.    R.Ubar, J.Raik. Efficient Hierarchical Approach to Test Generation for Digital Systems. 1st Int. Symp. on Quality of Electronic Design, San Jose, California, March 20-22, 2000, pp. 189-195.

70.    R.Ubar, A.Morawiec, J.Raik. Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. IEEE Proc. of  Design Automation and Test in Europe. Paris, March  27-30, 2000, pp. 743.

71.    M.Blyzniuk, FT.Cibakova, E.Gramatova, W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Defect-Oriented Fault Simulation for Digital Circuits. IEEE European Test Workshop, Cascais, Portugal, Mai 23-26, 2000, pp.151-156.

72.    R.Ubar, A.Morawiec, J.Raik. Back-Tracing and Event-Driven Techniques in High-Level Simulation with Decision Diagrams. Proc. of the IEEE ISCAS’2000 Conference, Geneva, May 28-31, 2000, Vol. 1, pp. 208-211.

73.    G.Jervan, Z.Peng, R.Ubar. Test Cost Minimization for Hybrid BIST. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems. Tokio, October 25-28, 2000, pp.283-291.

74.    R.Ubar, H.-D.Wuttke. Action Based Learning System for Teaching Digital Electronics and Test. In “Microelectronics Education”, Kluwer Academic Publishers, Dordrecht/ Boston/London, 2000, pp. 107-110.

75.    R.Leveugle, R.Ubar. Modeling VHDL Clock-Driven Multi-Processes by Decision Diagrams.  J. of Electron Technology, Vol. 32, (1999) No.3, pp.282-287.

76.     R.Ubar, D.Borrione. Single Gate Design Error Diagnosis in Combinational Circuits. Proceedings of the Estonian Acad. of Sci. Engng, 1999, Vol. 5 , No 1, pp.3-21.

77.     J.Raik, R.Ubar. Sequential Circuit Test Generation Using Decision Diagram Models. IEEE Proc. of  Design Automation and Test in Europe. Munich, March  9-12, 1999.

78.     R.Ubar, A.Moraviec, J.Raik. Cycle-based Simulation with Decision Diagrams. IEEE Proc. of  Design Automation and Test in Europe. Munich, March  9-12, 1999.

79.     R.Ubar. Combining Functional and Structural Approaches in Test Generation for Digital Systems. Journal of Microelectronics and Reliability, Elsevier Science Ltd. Vol. 38:3, pp.317-329, 1998.

80.     R.Ubar. Multi-Valued Simulation of Digital Circuits with Structurally Synthesized Binary Decision Diagrams. OPA (Overseas Publishers Assotiation) N.V. Gordon and Breach Publishers, Multiple Valued Logic, Vol.4  pp. 141-157, 1998.

81.     R.Ubar. Dynamic Analysis of Digital Circuits with 5-valued Simulation. In "Mixed Design of Integrated Circuits and Systems". Kluwer Academic Publishers, pp.187-192, 1998.

82.     M.Brik, G.Jervan, A.Markus, J.Raik, R.Ubar. Hierarchical Test Generation for Digital Systems. In "Mixed Design of Integrated Circuits and Systems". Kluwer Academic Publishers, pp.131-136, 1998.

83.     R.Ubar. Dynamic Analysis of Digital Circuits with Multi-Valued Simulation. Microelectronics Journal, Elsevier Science Ltd., Vol. 29, No. 11, Nov. 1998, pp.821-826.

84.     R.Ubar, D.Borrione. Generation of Tests for the Localization of Single-Gate Design Errors in Combinational Circuits Using the Stuck-at Fault Model. Proc. of the 11th IEEE Brasilian Symposium on Integrated Circuit Design. Rio de Janeiro, Brazil, Sept. 30 – Oct. 3, 1998, pp.51-54

85.     A. Benso, P.Prinetto, M.Rebaudengo, M.Sonza, R.Ubar. A New Approach to Build a Low-Level Malicious Fault List Starting from High-Level Description and Alternative Graphs. Proc. IEEE European Design& Test Conference, Paris, March 17-20, 1997, pp.560-565.

86.     R.Ubar, J.Raik. Multi-Valued Simulation with Binary Decision Diagrams. Proc.IEEE European Test Workshop, Cagliari (Italy), May 28-30, 1997, pp.28-29.

87.     R.Ubar. Representing Transparency Conditions in Test Generation for VLSI by Decision Diagrams. 1st Electronic Circuits and Systems Conference. Bratislava, September 4-5, 1997, pp.213-216.

88.     R.Ubar. Multi-Valued Simulation of Digital Circuits. Proc. of the IEEE 21st Int.  Conference on Microelectronics. Nis, Yugoslavia, September 14-17, 1997, pp. 721-724.

89.     A.Benso, P.Prinetto, M.Rebaudengo, M.Sonza Reorda, J.Raik, R.Ubar. Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Paris, October 20-22, 1997, pp. 212-216.

90.     M.Brik, G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. Mixed-Level Test Generator for Digital Systems. Proceedings of the Estonian Acad. of Sci. Engng, 1997, Vol. 3 , No 4, pp. 269-280.

91.     R.Ubar. Test Synthesis with Alternative Graphs. IEEE Design and Test of Computers. Spring, 1996, pp.48-59.

92.     R.Ubar, M.Brik. Multi-Level Test Generation and Fault Diagnosis for Finite State Machines. Lecture Notes in Computer Science No 1150. Dependable Computing - EDCC-2. Springer-Verlag, 1996, pp.264-281.

93.     R.Ubar, P.Paomets, J.Raik. Low-Cost CAD System for Teaching Digital Test. Microelectronics Education. World Scientific Publishing Co. Pte. Ltd. 1996, p.185-188.

94.     R.Ubar. Electronics Competence Centre and Research in Digital Test at Technical University of Tallinn. Invited paper. IEEE 14th NORCHIP Conference, Helsinki, November 4-5, 1996, pp.134-141.

95.     R.Ubar. Case Study in Testing Digital Systems. Invited paper. (Baltic Electronics, Vol. 1, No. 1, Sept. 1995, pp.24-27.

96.     R.Ubar. Fault Diagnosis in Digital Devices Proceedings of the Estonian Academy of Sciences, Engng, 1995, No. 1/1, pp.51-67.

97.     R.Ubar. Electronics Competence Centre as a Result of European Projects at the Technical University of Tallinn. Invited paper. Baltic Electronics, Vol. 1, No. 2, Dec., 1995, pp.9-11.

98.     R.Ubar. Test Generation for Digital Systems Based on Alternative Graphs Theory. Lecture Notes in Computer Science No 852. Dependable Computing - EDCC-1. Springer-Verlag, 1994, pp.151-164.

99.     R.Ubar, A.Buldas, P.Paomets, J.Raik, V.Tulit. A PC-based CAD System for Training Digital Test. Proc. 5th EUROCHIP Workshop on VLSI Design Training. Dresden, October 17-19, 1994, pp.152-157.

100. R.Ubar, K.Kuchcinski. Functional Level Testability Analysis for Digital Circuits. Proc. of European Test Conference ETC'93, Rotterdam, April 19-22, 1993, pp.545-546.

101. R.Ubar. Alternative Graph Based Test Design in Digital Systems. Invited paper. Proc. of the 11. NORCHIP Conference, Trondheim (Norway), Nov. 9-10, pp.48-62, 1993.

102. R.Ubar. Diagnostic Software for Systems. In "Concise Encyclopedia of Software Engineering". Pergamon Press, 1992, pp.101-106.

103. R.Ubar. Testing of systems using software. In "Concise Encyclopedia of Software Engineering". Pergamon Press, 1992, pp.354-357.

104. T.Lohuaru, R.Ubar. A set of tools for diagnosis of digital devices. PC World, Information Computer Enterprise, Moscow, No1, 1991, pp.122-125 (in Russian).

105. R.Ubar. Digital test design based on alternative graphs. Proc. of the 2nd European Design Automation Conference, Amsterdam, February 25-28, 1991.

106. R.Ubar, K.Kuchcinski, Z.Peng. Test generation of digital systems at functional level. The 2nd European Test Conference, Munich, Germany, April 10-12, 1991.

107. R.Ubar. An approach to develop intelligent digital test systems. Periodica Polytechnica Ser. Electrical Engineering, Budapest, Vol.34, No.4, pp.233-244, 1990.

108. R.Ubar. Functional Level Test Set Generation Methods. Invited paper. Proc. of the 12th Conf. on Fault-Tolerant Systems and Diagnostics, Prague, Sept.,1989, pp.46-55.

109. R.Ubar. Alternative Graphs and Technical Diagnosis of Digital Devices. Electronic Techniques, Vol.8, No.5 (132), 1988, Moscow, pp.33-57 (in Russian).

110. R.Ubar. Research and Development of Testing Methods for Digital Systems. DSc Dissertation. Institute of Electronics and Computer Science, Riga, 1986, 496p.

111. R.Ubar. Using Alternative Graphs for Automatization of Test Program Synthesis for Microprocessor LSI. Electronic Techniques Ser.8, 1985, Vol.5 (116), Moscow, pp.110-113.

112. R.Ubar. General Approach to Test Synthesis for Digital Circuits and Systems. Proc. of  the 10th All-Union Workshop on Technical Diagnostics, Tallinn, Oct., 1984, pp.75-81. (in Russian).

113. R.Ubar. Test Generation for Digital Systems on the Vector Alternative Graph Model. Proc. of the 13th International Symp. on Fault Tolerant Computing, Milano, Italy, 1983, pp.374-377.

114. T.Lohuaru, M.Pall, R.Ubar. Automated Test Synthesis for Fault Diagnosis in Digital Devices. Journal of Academy of Sciences of Estonia, Vol.32, Phys.& Math., 1983, No.1, pp.84-94 (in Russian).

115. R.Ubar. Generation of Complete Tests for Combinational Circuits. Journal of Academy of Sciences of Estonia, Vol.31, Phys.& Math., 1982, No.4, pp.418-427 (in Russian).

116. R.Ubar. Vektorielle Alternative Graphen und Fehlerdiagnose für digitale Systeme. Nachrichtentechnik/Elektronik, (31) 1981, H.1, pp.25-29.

117. M.Plakk and R.Ubar.Test Generation for Digital Circuits by Alternative Graphs. Automatics and Telemechanics, No.5, 1980, Moscow, pp.152-163 (in Russian).

118. R.Ubar. Beschreibung Digitaler Einrichtungen mit Alternativen Graphen für die Fehlerdiagnose. Nachrichtentechnik/Elektronik, (30) 1980, H.3, pp.96-102.

119. M.Plakk, R.Ubar. Digital Circuit Test Design using the Alternative Graph Model. Automation and Remote Control, Vol.41, No 5, part 2,  Nov. 1980, Plenum Publishing Corporation, USA, pp. 714-722.

120. R.Ubar. Detection of Suspected Faults in Combinational Circuits by Solving Boolean Differential Equations Automation and Remote Control, Vol.40, No 11, part 2,  Nov. 1980, Plenum Publishing Corporation, USA, pp. 1693-1703.

121. R.Ubar. Fault Diagnosis in Combinational Circuits by Solving Boolean Differential Equations. Automatics and Telemechanics, No.11, 1979, Moscow, pp.170-183 (in Russian).

122. R.Ubar. Analysis of Diagnostic Tests for Combinational Circuits by Method of Backtracking of Faults. Automation and Remote Control, Vol.40, No.11, part 2, Nov. 1978. Plenum Publishing Corporation, USA, pp. 1254-1260.

123. R.Ubar. Berechnung von Boole'schen Ableitungen bei der Testsatzanalyse für digitale Schaltungen. Nachrichtentechnik/Elektronik, 1977, H.1, s.21-23.

124. R.Ubar. Analysis of Diagnostic Tests for Combinational Circuits by the Method  of Fault Backtracing. Automatics and Telemechanics, No.8, 1977, Moscow, pp.168-176 (in Russian).

125. R.Ubar. Multiple Fault Analysis in Logic Circuits. Proc. of the IFAC Symposium on Discrete Systems, Dresden, 1977, Band 4, pp.48-57.

126. R.Ubar. Test Generation for Digital Circuits with Alternative Graphs. Proceedings of Tallinn Technical University, No.409, 1976, Tallinn, pp.75-81 (in Russian).

127. Simulating System for Minicomputer Diagnostic Programs. (P.  Kitsnik,  R. Ubar, A.Viilup),  Preprints of IFAC/IFIP 1st Int.  Symp.,  Tallinn, August, 1976, pp.115-117.

 

c) autoritunnistused

  1. Equipment for Testing LSI. (T. Lohuaru and R.Ubar), A.C. No.1218390, Inf. Bull. No.10, 1986.
  2. Equipment  for  Testing  Synchronized  digital   circuits.  (T.Evartson, R.Ubar, A.Viilup), A.C. No.3772884/24, Inf. Bulletin No.25, 1986.
  3. Equipment for Fault Localization in Digital Objects. (T.Evartson, H.Haak, T.Lohuaru, R.Ubar), A.C. No.3984709/24, Inf. Bulletin No.19, 1987.
  4. Equipment for testing  VLSI.  (T.Lohuaru,  M.Männisalu,  P.Pukk,  R.Ubar, E.Vanamölder). A.C. No. SU 1652976 A1, Inf. Bulletin No.20, 1991.

 

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