Lab 4

Model of elevator controller with direction detection

 

The purpose of this lab is to become acquainted with Verilog hardware description language. There is no difference in compilation and simulation of Verilog files compared to VHDL files using ModelSim simulator. There is difference using Synopsys simulator such as:

·        To compile your design type:

vcs –RI +v2k mux.v t_mux.v

this command opens also Scirocco graphical simulator

·         Flag –RI creates an executable simulator in your current directory and starts the simulator, also opens GUI

·         Flag +v2k allows to compile old Verilog syntaxes from year 2000 (default compiler is from standard year 2003)

·        To run the simulation in the Interactive window of Scirocco simulator in the field Simulator Control choose Go To Time option, type amount of time you want to run the simulation and press OK

To put time units of Verilog code correctly use either:

  • `timescale {the smallest unit of time you use}/{resolution} in your Verilog code before the module declaration Example: `timescale 1 s/10 ms
  • or during loading the simulation specify option –t to fix the smallest time unit of your design. Example: vsim –t 1 sec work.t_elevator

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    In order to practice how to compile and simulate Verilog files in available simulators design of multiplexer mux.v written in Verilog is given for you, also the testbench for the multiplexer is proposed t_mux.v.

     

    During this lab you should rewrite your elevator controller designed in lab 3 from VHDL language to Verilog language. Beside that you need to add some more functionality to the elevator controller. In particular, user, who is outside the lift car can choose the direction he/she wants to go. In order to fulfill this requirement BUTTONS_OUT input vector is divided into 2 vectors: BUTTONS_OUT_UP and BUTTONS_OUT_DN, where

    ·        BUTTONS_OUT_UP denotes user wants to go up when he/she will get into the lift car, therefore if elevator is going down it should not stop at this floor;

    ·        BUTTONS_OUT_DN denotes user wants to go down when he/she will get into the lift car, therefore if elevator is going up it should not stop at this floor.

     

     General block scheme of the elevator controller is given below:


     

    For this task you firstly get an “empty module” of the model of elevator controller (the specification is the same as in the lab 3) – design interface elevator.v, which you need to fill with behavioral design of elevator controller. To test your design correctness, ready-made simple testbench t_elevator.v is given. Then “empty module” of extended model of elevator controller is proposed to you – design interface elevator2.v, into which you copy all your previous design and add functionality. To test your extended design correctness, ready-made simple testbench t_elevator2.v is given.

     

    Task:

     

    ·        Learn to use available simulators for Verilog files, compile and simulate given multiplexer design.

    ·        Rewrite the behavioral model of elevator from VHDL to Verilog (supposed the lab 3 is ready). Simulate your design in order to get correct behavior of the elevator.

    ·        Add described above functionality, so that it could be possible to call the elevator from outside giving desirable direction. Simulate your design in order to get correct behaviour of the elevator.

     

    Requirements:

    ·        Code with comments added to the report;

    ·        Waveform picture added to the report;

    ·        Description of the solution.