Lab 1

The purpose of this lab is to become acquainted with synthesis tools of Mentor Graphics LeonardoSpectrum and Synopsys. To get familiar with the tools VHDL files of one-directional counter counter.vhd and testbench for it t_counter.vhd are offered to you. First of all you need to control the behaviour of the counter with your favourite simulation tool. The required behaviour is the following:

• All actions of counter must occur at rising edge of clock signal clock;
• It is allowed to count only in case the enable signal is ‘1’, otherwise the counting must stop;
• The load of the counter with initial value from port start_address only occurs when the input signal reset is ‘1’;
• The counting must stop, when it has arrived to the value from port stop_address;
• The size of counter in bits is defined with parameter bitwidth.

The scematic diagram of counter is depicted in the Figure 1.

Figure1. Scematic diagram of the counter

Similar counters are used for example in video processing for generation the interval of addresses during memory access, where specific hardware creation is ecpecially more useful (delay, area and/or performance) than universal counter usage.

It is possible to design counters and other devices with many different styles. Even if simulation results of different design styles are the same, this still doesn’t mean that synthesize hardware would be the same. The reason is single structures are mostly considered during synthesis, not module as entire behaviour. During this lab you are going to synthesize given one-directional counter counter.vhd. Afterwards your task is to modify existing one-directional counter to two-directional counter and to synthesize it.

Tasks:

1. Simulation and synthesis of given one-directional counter

· Take one-directional counter design in RTL style counter.vhd proposed to you and simulate it with any simulator in order to certain correct behaviour of it (counter must increase the value by one from start_address and stop when it reaches stop_address and correspond to the specification above). Ready testbench is given to you t_counter.vhd;

· Take the guide for Sysnopsys synthesis tool and synthesize counter.vhd design with clock frequency 50 MHz and with parameter bitwidth=4. Analyse the synthesize results (scheme, area data, timing data). Put in the report area size, delay and the largest possible clock frequency for this design;

· Take the guide for Xilinx ISE synthesis tool and repeat all subtasks from previous point;

· In existing design two registers are used for every bit. If we look at the VHDL code counter.vhd, where it comes from? Change the design so that only one register is used for every bit. Synthesize modified design to make sure of correct solution. (clue: during the simulation there should not be delay in one clock cycle when counter starts to increase it’s value. Why?).

1. Simulation and synthesis of two-directional counter

· Modify one-directional counter so that it could be possible to count both directions. The condition is the following: if start_address is larger than stop-address, then counter counts down, otherwise up and stops when reaches stop_address value. Simulate the design (use the same testbench) and analyze the results.

· Synthesize two-directional counter design with clock frequency 50 MHz and with parameter bitwidth=4. Analyse the synthesize results (scheme, area data, timing data). Put in the report area size, delay and the largest possible clock frequency for this design;