The xtimport
tool is used in the Design Error Diagnosis laboratory
work to generate the specification (<design>.spec) and the implementation
(<design>.agm). It also prodvides some additional information about the
circuit (<design>.pat, <design>.gat) to the prediag
tool. The implementation is obtained in the following way (take a look at this
log and at the comments given in between of two * (stars):
prompt> xtimport -paths c17.edi bench.lib | *use -paths option to save needed info* |
SSBDD Synthesis
from EDIF 2.0.0 Netlist, Extended Version Loading EDIF... OK Loading library file... OK Creating output file... OK Searching for top level designs... OK c17_lib Design: c17 Reading ports... OK Reading instances... OK Connecting nets... OK Converting... Deleting redundant lines... OK Generating names... OK Creating simulation order... OK Generating SSBDD model... OK Saving info about
gate-level signal paths... OK |
|
Success! | *so, everything is okay* |
The specification
is obtained using -spec option
instead of -paths option (do
not use two options simultaneously!).
prompt> xtimport -spec c17.edi bench.lib | *use -spec option to obtain the specification* |
SSBDD Synthesis
from EDIF 2.0.0 Netlist, Extended Version Loading EDIF... OK Loading library file... OK Creating output file... OK Searching for top level designs... OK c17_lib Design: c17 Reading ports... OK Reading instances... OK Connecting nets... OK Converting... Deleting redundant lines... OK Generating names... OK Creating simulation order... OK Generating specification model... OK The encrypted name of the modified gate is Y{ABD7`*H{{M\LTS%Hy5)flYyj3S* Saving encrypted
name... OK Success! |
At this step, the xtimport
tool creates a report file c17.rep
and saves the encrypted info about the error type and location there. Later,
the other programs, used in the laboratory work will also save needed info in
this file. Therefore, when the work is done, all you have to show to the teacher
is stored in this file.
prompt> more c17.rep | |
Report File for the Lab Work on Design Error Diagnosis Encrypted name of the modified gate is Y{ABD7`*H{{M\LTS%Hy5)flYyj3S* |
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Last update: 28 July, 2004