Usage of the Extended Netlist Interface

xtimport is an extended version of the import tool. It has all the functionality of import but includes some additional features. It has been designed specially for "Design Error Diagnosis" practical work. It allows to create an implementation and specification. Here, the specification is the same design as implementation but with randomly changed function of a randomly chosen gate. Specification can be created using -spec option. Specification is always a gate-level SSBDD model. When creating the specification, the xtimport tool creates also a report file (<design>.rep), where stores, as encrypted data, the information about the gate, whose function had been changed. Some data about gate-level signal paths must be also preserved during generation of the implementation in order to allow the prediagnostic tool work. This data is saved using the flag -paths.
 

command: xtimport

input: EDIF or ISCAS'89 netlist file
output:
 		 specification (.spec), implementation (.agm), gate-level paths (.gat),
gate names and types (.pat), report file (.rep), technology library file or ISCAS'85 model file (.cir).
 
syntax:

xtimport [options] <EDIF file> <library file>
 
options:  
-paths Preserve information about gate-level signal paths.
-spec Create a specification (insert a design error).
-gate_level
Generate gate-level SSBDD model (default: macro-level SSBDD model).
-tool <application>
Options for 'application' are orcad and cadence.
-gnd <ground> Specify the ground net name
-vdd <voltage> Specify the VDD net name
-clock <pinName> Specify the clock net name
-lib_cell Generate TT library format output
-iscas85 Generate ISCAS'85 output (do not use with -read_iscas89 option!).
-general Generate general (high-level) DD-model


Error Messages and Warnings

The netlist interface displays error messages and warnings about possible failures while parsing the EDIF netlist file. Line numbers of the input netlist file where errors occurred are provided. Pay attention to ALL of the displayed errors and warnings if the program terminates abnormally!

Note that some of the warnings should be ignored, however. For example, one of the most common warnings during reading a hierarchical design is as follows:

Design: COMPONENT_1
Parsing macro

Warning at line 1917: Gate not in library

This warning shows that there exists a cell named COMPONENT_1 in the EDIF description. It either means that COMPONENT_1 is a block in the hierarchy, or it is a cell, which is not specified in the technology library. In the first case, the warning should be ignored. In the latter case, EDIF parsing fails due to an incompletely specified technology library and the cell COMPONENT_1 should be included to the library.

Construction of an Abstract Network

Last update: 28 July, 2004