Cadence Design Interface

Overview

In order to generate an EDIF output compatible with Turbo Tester EDIF Interface, select File|Export|EDIF 200... (see the Cadence documentation for information on how to fill the EDIFOUT form window). However, there are some additional requirements.

Requirements

1. Design Name mus be specified!
   
   The name can be arbitrary. It is only needed to force EDIFOUT to identify the cell containing top-level design.
2. External Libraries should be left blank
3. Ripper Library Name, Ripper Cell Name and Ripper View Name should be set to basic, patch and symbol, respectively. These are also default values for EDIFOUT.
4. Netlist Only option should be turned on to exclude all graphic information and to reduce the size of output file.
5. Both, hierarchical and flattened netlists are supported.

Cadence schematic editor is not case sensitive, but Turbo tester EDIF Interface is. Therefore do not use similar names with different capitalization, e.g. A1 and a1, for ports and instances in your schematic.

Where have we been?

• Introduction
• Features
• Getting Started
• Troubleshooting
• Appendixes

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