Includes test generators, logic and fault simulators, test optimizer, a
module for hazard analysis, BIST
architecture simulators, design verification and design error diagnosis
tools.
Contact person: Jaan Raik
Integrated circuit and a measurement environment for experimental study of
CMOS defects. It includes an educational IC with a large variety of shorts and
opens physically inserted into a set of simple digital circuits. DefSim
supports two measurement modes - voltage and IDDQ test.
Contact person: Artur Jutman
Training system aimed at teaching main (both basic and advanced) principles
and techniques applied in Built-in Self-Testing (BIST)
of modern multi-core electronic systems. It facilitates study of various
test optimization problems, allows fault coverage analysis for various test
generation and optimization parameters.
Contact person: Anton Tsertov antonchertov@gmail.com
Multi-functional software system, which provides simulation, demonstration,
and CAD environment for learning, research,
and development related to IEEE 1149.1 Boundary Scan standard. It supports
important Boundary Scan data formats (BSDL, SVF)
through which it can interact with other BS development tools. It allows a
visual design and simulation of BS-enabled chips, non-BS clusters and whole
boards. It is also possible to simulate the behavior of various interconnect
faults and inspect them using interactive tools.
Contact person:Artur Jutman
Java applet for learning and teaching basic principles for logic level test
generation, fault simulation and fault diagnosis. The software provides easy action
and reaction (click and watch), the possibility of distance learning, and
learning by doing.
Contact person: Elmet Orasson
Java applet for simulation, test generation and test grading for digital
systems at register transfer level. Traditional functional test, built-in-self
test (BIST) and functional BIST learning and research is supported.
Contact person: Sergei Devadze <serega@pld.ttu.ee>
Multi-functional software system, which provides simulation, demonstration,
and CAD environment for learning the possibilities of IEEE 1149.1 Boundary Scan
test standard.
Contact person: Artur Jutman