Topic: Design for Testability - Laboratory work 4

1. Test Generation 2. Design Error Diagnosis 3. Built-in Self-Test 4. Design for Testability 4.1. Example

 

4. DESIGN FOR TESTABILITY

Objectives
To show how the controllability and the observability can improve the fault coverage. To learn exploiting the controllability and the observability in test generation. To find the best combination of controllability and observability for a certain circuit.
 

Introduction
The testability is one of the most important requirements which should be considered along with other essential constraints such as performance or cost when designing a circuit. The circuit with poor testability causes big time and/or cost losses during post-fabrication testing and testing for serviceability. The latter aspect might be very important because the testing for serviceability of some operation-critical devices is done during the whole lifetime of such a device. Hence, there are many different methods and techniques worked out aimed at improving the testability of complex circuits and systems. The simplest way to add a testability to a device is to insert additional pins connected to some control points inside the device in order to control and/or to observe the internal processes.
 

Work description
In this work we are going to examine the system consisting of two complex units connected in series i.e. the output of the first unit is connected in a complex manner to the inputs of another unit. Both units are the same adders from the Test Generation laboratory work. The interconnection between these units is not designed so, that the observability and the controllability of the whole system is good enough. This results in an unsatisfactory testability (low fault coverage) of the system. Let's suppose, that in order to improve the situation the test engineers proposed several modifications of the original system. All modifications utilize different Design-for-Testability (DFT) techniques or their combinations. The following options are available:

• Original circuit without any DFT facilities
• Observable circuit. The output of the first unit is observable (two modifications)
• Controllable circuit. The inputs of the second unit are controllable
• Testable system. Both the observability and the controllability facilities are embedded (also two modifications)

Our task in this work is to study all the available solutions and decide which one is the best one. Our goal is to select a solution, which provides 100% fault coverage combined with a short test and a cheap DFT hardware implementation. The hardware complexity (in this work) will be measured in the number of additional I/O pins. In fact, different solutions might have different efficiency with different test application techniques. Therefore, we are going to select proper DFT solution for two different testing approaches: the ATE (automatic test equipment) approach with deterministic ATPG patterns and the BIST approach with pseudo-random patterns coming out of the LFSR. We will compare different solution by calculating their cost using the following equation:

Cost = a·C_h + b·C_v

a and b are to be chosen so that one I/O pad had the same cost as 5 test vectors.
 

Steps

1. Using the deterministic ATPG generate tests for the original design, the controllable circuit, and for all the modifications of observable and testable circuits. Fill in the following table:
    

   TABLE 1

   	Original Design	Observable Circuit I	Observable Circuit II	Controllable Circuit	Testable Circuit I	Testable Circuit II
   No. of I/O Pads (inputs+outputs)
   Number of Test Vectors
   Fault Coverage, [%]
   No. of Tested Faults
   Cost

   
    
2. The testability can be measured by the fault coverage (or by the number of untestable faults) as well as by the test length or by the test generation time. Compare the results obtained by the ATPG for all modifications of the circuit. Calculate the cost.
3. Apply the BIST emulator (in BILBO mode) to all the circuits. Note, that they have different number of inputs and therefore the BIST architecture should be also different. Actually, we will need two different architectures: one for the original design and for both observable circuits (because they have the same number of inputs and we evaluate only the TG of BILBO) and another one for the controllable and for both testable circuits. Make several experiments with different random LFSR configurations (10-15 at least). Fill in the following tables with the best results you have received:
    

   TABLE 2

   	Original Design	Observable Circuit I	Observable Circuit II
   No. of I/O Pads (inputs+outputs)
   Number of Test Vectors
   Fault Coverage, [%]
   No. of Tested Faults
   Cost

    
   

   TABLE 3

   	Controllable Circuit	Testable Circuit I	Testable Circuit II
   No. of I/O Pads (inputs+outputs)
   Number of Test Vectors
   Fault Coverage, [%]
   No. of Tested Faults
   Cost

    
   
4. Calculate the cost and compare the results obtained with the LFSR emulator for all the circuits.

4.1 Example

The usage of the deterministic ATPG was considered in the Test Generation laboratory work. The description and the usage of the BIST emulator were given in the Built-in Self Test laboratoy work. The corresponding examples are discussed as well.

Last update: 18 February, 2004 by Artur Jutman