| Title | PERFORMANCE AND ENERGY EVALUATION OF NVM-BASED CIM AND MEMORY HIERARCHY |
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| Authors | Ameer Shalabi |
| Coference | --- |
| Abstract | Non-Volatile Memory technologies are rapidly rising as the most promising candidate for universal memory technologies. NVMs are characterized with low-power leakage, high density storage, and fast access time. NVMs offer solutions for the high standby mode power consumption that contemporary memory technologies suffer from. Furthermore, such NVMs can be programmed and designed to create NVM-based arrays capable of completing complex logical operations as Computation in Memory. In this thesis, the Level-1 instructions cache is augmented with a Non-Volatile Scratch Pad that stores instructions that cause highest number of I-cache misses. When implementing the NV-SP using Magnetic RAM, it improved the performance for all the simulated applications at different sizes. Performance improvement reached up to 22% for applications with the highest miss rate. The MRAM NV-SP has been shown to improve the total access energy and total power leakage of the I-cache. However, when such NV-SP is implemented using PCRAM, it showed that it can cause performance degradation for application with low miss latency at large NV-SP sizes. It is also showed that PCRAM had reduced the total access energy of the I-cache for all the applications at all sizes, but increased the power leakage of the I-cache at larger NV-SP sizes. Furthermore, this thesis also presents an implementation of a memristor-based AES S-Box. Such implementation uses memristor-based AND, OR, and XOR logic gates that perform Computation in Memory. | Access | Master of Science - Computer and Systems Engineering Thesis - PDF direct download |
| Title | NV-SP: A New High Performance and Low Energy NVM-Based Scratch Pad |
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| Authors | Ameer Shalabi, Kolin Paul, Tara Ghasempouri, Jaan Raik |
| Coference | IEEE Computer Society Annual Symposium on VLSI (ISVLSI) -- June, 2020 |
| Abstract | Non-Volatile Memory technologies are rising as a candidate for a universal memory. NVMs offer solutions for the high power consumption that contemporary memory suffers from. Hence, we propose augmenting the traditional SRAM cache with an additional NVM device instead of entirely replacing SRAM with NVM. The L1 instruction-cache is augmented with a Non-Volatile Scratch-Pad, coined NV-SP, that stores instructions causing the highest number of misses. Experiments were evaluated for performance and energy of the SRAM I-cache and the NV-SP when implemented using Magnetic RAM and Phase-Changing RAM technologies. Results have shown that MRAM NV-SP had effectively improved the performance of the I-cache. | Access | PDF , ISVLSI video presentation |
| Title | SCAAT: Secure Cache Alternative Address Table for mitigating cache logical side-channel attacks |
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| Authors | Ameer Shalabi, Tara Ghasempouri, Peeter Ellervee, Jaan Raik |
| Coference | Euromicro Conference on Digital System Design (DSD) -- August, 2020 |
| Abstract | Interest in memory systems' security has increased during the last decade due to their vulnerabilities to be exploited by logical side channels attacks. A promising approach for attack detection at run-time is to monitor the cache memory's behavior. However, designing an environment capable of detecting and mitigating these attacks is very challenging. In current monitoring systems, attack mitigation has been largely neglected. To overcome these shortcomings, in this work, we present a secure cache called SCAAT. SCAAT is equipped with an attack mitigation system to handle attacks by remapping where data is stored in the cache to random locations. In addition, SCAAT uses an attack monitor that identifies suspicious behavior that indicates cache logical side-channel attacks. The effectiveness of SCAAT is analyzed and evaluated for several cache configurations in terms of area overhead and performance. | Access | PDF, DSD video presentation |