There are a lot of experiments to be conducted throughout the laboratory course. To help you with your experimental data systematization we have composed a number of standard fill-out forms with all the needed tables. Your task is just to carefully fill in those tables with the data. The laboratory works can be then defended based just on these filled in forms. The following forms are available:

• Test Generation work
• Built-In Self-Test work
• Design for Testability work
• Defsim - Study of Real CMOS Defects

For the Design Error Diagnosis work just print out the circuit schematic and mark upon it the steps of the diagnosis: the vectors that you generated and the diagnostic results. You can also add the <design>.rep file, which is generated automatically. Circuit schematics for printing out are available here:

• Test Generation work - t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, adder
• Design Error Diagnosis work - d1, d2, d3, d4, d5, d6, d7, d8, d9, d10

Last update:  20 November, 2006